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PIC12F/LF1822/PIC16F/LF1823 Data Sheet
8/14-Pin Flash Microcontrollers with nanoWatt XLP Technology
2010 Microchip Technology Inc.
Preliminary
DS41413A
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-051-5
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS41413A-page 2
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
8/14-Pin Flash Microcontrollers with nanoWatt Technology
High-Performance RISC CPU:
* Only 49 Instructions to Learn: - All single-cycle instructions except branches * Operating Speed: - DC - 32 MHz oscillator/clock input - DC - 125 ns instruction cycle * Interrupt Capability with Automatic Context Saving * 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset * Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory
Low-Power Features:
* Standby Current (PIC12LF1822/16LF1823): - 30 nA @ 1.8V, typical * Operating Current (PIC12LF1822/16LF1823): - 75 A @ 1 MHz, 1.8V, typical * Low-Power Watchdog Timer Current (PIC12LF1822/16LF1823): - 500 nA @ 1.8V, typical
Analog Features:
* Analog-to-Digital Converter (ADC) module: - 10-bit resolution, up to 8 channels - Conversion available during Sleep * Analog Comparator module: - Up to two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis * Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection
Flexible Oscillator Structure:
* Precision 32 MHz internal Oscillator Block: - Factory calibrated to 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz * 31 kHz Low-Power Internal Oscillator * Four crystal modes up to 32 MHz * Three external clock modes up to 32 MHz * 4X Phase Lock Loop (PLL) * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops * Two-Speed Oscillator Start-up * Reference Clock Module: - Programmable clock output frequency and duty-cycle
Peripheral Highlights:
* Up to 11 I/O pins and 1 input only pin: - High current sink/source 25 mA/25 mA - Programmable weak pull-ups - Programmable interrupt-on-change pins * Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler * Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver * Timer2: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler * Enhanced CCP (ECCP) modules: - Software selectable time bases - Auto-shutdown and auto-restart - PWM steering * Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility * Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module: - RS-232, RS-485 and LIN compatible - Auto-Baud Detect * mTouchTM Sensing oscillator module: - Up to 8 input channels
Special Microcontroller Features:
* * * * * * * * * * Full 5.5V operation - PIC12F1822/16F1823 1.8V-3.6V operation - PIC12LF1822/16LF1823 Self-reprogrammable under software control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT) In-Circuit Serial ProgrammingTM (ICSPTM) via two pins In-Circuit Debug (ICD) via two pins Enhanced Low-Voltage Programming (LVP) Operating Voltage Range: - 1.8V-5.5V (PIC12F1822/16F1823) - 1.8V-3.6V (PIC12LF1822/16LF1823) Programmable Code Protection Self-Programmable under Software Control
* *
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 3
PIC12F/LF1822/16F/LF1823
Peripheral Features (Continued):
* Data Signal Modulator module - Selectable modulator and carrier sources * SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications
PIC12F/LF1822/16F/LF1823 Family Types
ECCP (Half-Bridge) 1 1 -- -- ECCP (Full-Bridge) Timers (8/16-bit) 10-bit ADC (ch) CapSense (ch) Comparators Program Memory Device Words Data Memory Data EEPROM (bytes) I/O's(1) SRAM (bytes)
PIC12LF1822 2K 128 PIC12F1822 2K 128 PIC16LF1823 2K 128 PIC16F1823 2K 128 Note 1: One pin is input only.
256 256 256 256
6 6 12 12
4 4 8 8
4 4 8 8
1 1 2 2
2/1 2/1 2/1 2/1
1 1 1 1
1 1 1 1
-- -- 1 1
Yes Yes Yes Yes
DS41413A-page 4
Preliminary
2010 Microchip Technology Inc.
SR Latch
EUSART
MSSP
FIGURE 1:
8-PIN DIAGRAM FOR PIC12F/LF1822
8-Pin PDIP/SOIC/DFN
Comparator
Cap Sense
Modulator
Reference
SR Latch
EUSART
Interrupt
Pull-up
Timers
MSSP
ECCP
RA0 RA1 RA2 RA3 RA4 RA5
7 6 5
AN0 AN1 AN2
DACOUT VREF --
CPS0 CPS1 CPS2
C1IN+ C1IN0C1OUT
-- SRI SRQ
-- -- T0CKI
P1B(1) -- CCP1(1) P1A(1) FLT0 -- P1B(1)
TX(1) CK(1) RX(1) DT(1) --
SDO(1) SS(1) SCL SCK SDA SDI SS(1) SDO(1)
IOC IOC INT/ IOC IOC IOC
MDOUT MDMIN MDCIN1
Y Y Y
ICSPDAT ICDDAT ICSPCLK ICPCLK --
4 3
-- AN3
-- --
-- CPS3
-- C1IN1-
-- --
T1G(1) T1G(1) T1OSO T1CKI T1OSI -- --
-- TX(1) CK(1) RX(1) DT(1) -- --
-- MDCIN2
Y Y
MCLR VPP OSC2 CLKOUT CLKR OSC1 CLKIN VDD VSS
2 1 8
-- -- --
-- -- --
-- -- --
-- -- --
SRNQ -- --
CCP1(1) P1A(1) -- --
-- -- --
IOC -- --
-- -- --
Y -- --
VDD VSS
Note 1: Pin function is selectable via the APFCON register.
Basic
A/D
I/O
2010 Microchip Technology Inc.
PDIP, SOIC, DFN
VDD RX(1)/DT(1)/CCP1(1)/P1A(1)/SRNQ/T1CKI/T1OSI/OSC1/CLKIN/RA5 MDCIN2/T1G(1)/P1B(1)/TX(1)/CK(1)/SDO(1)/CLKR/C1IN1-/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/VPP/T1G(1)/SS(1)/RA3 VSS RA0/AN0/CPS0/C1IN+/DACOUT/TX(1)/CK(1)/SDO(1)/SS(1)/P1B(1)/MDOUT/ICSPDAT RA1/AN1/CPS1/VREF/C1IN0-/SRI/RX(1)/DT(1)/SCL/SCK/MDMIN/ICSPCLK RA2/AN2/CPS2/C1OUT/SRQ/T0CKI/CCP1(1)/P1A(1)/FLT0/SDA/SDI/INT/MDCIN1
1 2 3 4
8 7 6 5
Note
1:
Pin function is selectable via the APFCON register.
TABLE 1:
8-PIN ALLOCATION TABLE (PIC12F/LF1822)
PIC12F/LF1822/16F/LF1823
Preliminary
DS41413A-page 5
FIGURE 2:
14-PIN DIAGRAM FOR PIC16F/LF1823
3 4 5 6 7
MCLR/VPP/T1G(1)/SS(1)/RA3 MDCIN2/RX
(1)/DT(1)/CCP1/P1A/RC5
PIC16F/LF1823
DS41413A-page 6
PIC12F/LF1822/16F/LF1823
PDIP, SOIC, TSSOP
VDD T1CKI/T1OSI/OSC1/CLKIN/RA5 T1G(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4
1 2
14 13 12 11 10 9 8
VSS RA0/AN0/CPS0/C1IN+/DACOUT/TX(1)/CK(1)/ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF/SRI/RX(1)/DT(1)/ICSPCLK RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/FLT0 RC0/AN4/CPS4/C2IN+/SCL/SCK RC1/AN5/CPS5/C12IN1-/SDA/SDI RC2/AN6/CPS6/C12IN2-/P1D/SDO(1)/MDCIN1
MDOUT/TX(1)/CK(1)/P1B/SRNQ/C2OUT/RC4 MDMIN/SS
(1)/P1C/C12IN3-/CPS7/AN7/RC3
Preliminary
2010 Microchip Technology Inc.
Note 1: Pin function is selectable via the APFCON register.
FIGURE 3:
QFN
14-PIN DIAGRAM FOR PIC16F/LF1823
5
6
7
MDCIN1/SDO(1)/P1D/C12IN2-/CPS6/AN6/RC2
MDOUT/TX(1)/CK(1)/P1B/SRNQ/C2OUT/RC4
Note 1:
Pin function is selectable via the APFCON register.
MDMIN/SS(1)/P1C/C12IN3-/CPS7/AN7/RC3
SDI/SDA/C12IN1-/CPS5/AN5/RC1
8
2010 Microchip Technology Inc.
VDD
16
15
14
13
VSS
NC
NC
T1CKI/T1OSI/OSC1/CLKIN/RA5 T1G(1)/SDO(1)/CLKR/T1OSO/CLKOUT/OSC2/CPS3/AN3/RA4 MCLR/VPP/T1G(1)/SS(1)/RA3 MDCIN2/RX(1)/DT(1)/CCP1/P1A/RC5
1 2 PIC16F/LF1823 3 4
12 11 10 9
RA0/AN0/CPS0/C1IN+/DACOUT/TX(1)/CK(1)/ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF/SRI/RX(1)/DT(1)/ICSPCLK RA2/AN2/CPS2/T0CKI/INT/C1OUT/SRQ/FLT0 RC0/AN4/CPS4/C2IN+/SCL/SCK
PIC12F/LF1822/16F/LF1823
Preliminary
DS41413A-page 7
PIC12F/LF1822/16F/LF1823
TABLE 2:
14-Pin PDIP/SOIC/TSSOP
14-PIN ALLOCATION TABLE (PIC16F/LF1823)
Comparator
16-Pin QFN
Cap Sense
Modulator
Reference
SR Latch
EUSART
Interrupt
Pull-up
Timers
MSSP
ECCP
RA0 RA1 RA2 RA3 RA4
13 12 12 11 11 10 4 3 3 2
AN0 AN1 AN2 -- AN3
DACOUT VREF -- -- --
CPS0 CPS1 CPS2 -- CPS3
C1IN+ C12IN0C1OUT -- --
-- SRI SRQ -- --
-- -- T0CKI T1G(1) T1G(1) T1OSO T1CKI T1OSI -- -- -- -- -- -- -- --
-- -- FLT0 --
TX(1) CK(1) RX(1) DT(1) -- -- --
-- -- -- SS(1) SDO(1)
IOC IOC INT/ IOC IOC IOC
-- -- -- -- --
Y Y Y Y Y
ICSPDAT ICDDAT ICSPCLK ICDCLK -- MCLR VPP OSC2 CLKOUT CLKR OSC1 CLKIN -- -- -- -- -- -- VDD VSS
RA5 RC0 RC1 RC2 RC3 RC4 RC5 VDD VSS Note 1:
2 10 9 8 7 6 5 1
1 9 8 7 6 5 4 16
-- AN4 AN5 AN6 AN7 -- -- -- --
-- -- -- -- -- -- -- -- --
-- CPS4 CPS5 CPS6 CPS7 -- -- -- --
-- C2IN+ C12IN1C12IN2C12IN3C2OUT -- -- --
-- -- -- -- -- SRNQ -- -- --
-- -- -- P1D P1C P1B CCP1 P1A -- --
-- -- -- -- -- TX(1) CK(1) RX(1) DT(1) -- --
-- SCL SCK SDA SDI SDO(1) SS(1) -- -- -- --
IOC -- -- -- -- -- -- -- --
-- -- -- MDCIN1 MDMIN MDOUT MDCIN2 -- --
Y Y Y Y Y Y Y -- --
14 13
Pin function is selectable via the APFCON register.
DS41413A-page 8
Preliminary
2010 Microchip Technology Inc.
Basic
A/D
I/O
PIC12F/LF1822/16F/LF1823
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 19 3.0 Memory Organization ................................................................................................................................................................. 21 4.0 Device Configuration .................................................................................................................................................................. 49 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 55 6.0 Reference Clock Module ............................................................................................................................................................ 71 7.0 Resets ........................................................................................................................................................................................ 75 8.0 Interrupts .................................................................................................................................................................................... 83 9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 95 10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 99 11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 103 12.0 I/O Ports ................................................................................................................................................................................... 117 13.0 Interrupt-on-Change ................................................................................................................................................................. 127 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 131 15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 133 16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 147 17.0 SR Latch................................................................................................................................................................................... 153 18.0 Comparator Module.................................................................................................................................................................. 159 19.0 Timer0 Module ......................................................................................................................................................................... 169 20.0 Timer1 Module ......................................................................................................................................................................... 172 21.0 Timer2 Modules........................................................................................................................................................................ 184 22.0 Data Signal Modulator (DSM) .................................................................................................................................................. 189 23.0 Capture/Compare/PWM Module .............................................................................................................................................. 199 24.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 225 25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 279 26.0 Capacitive Sensing Module...................................................................................................................................................... 307 27.0 In-Circuit Serial ProgrammingTM (ICSPTM) ................................................................................................................................ 315 28.0 Instruction Set Summary .......................................................................................................................................................... 319 29.0 Electrical Specifications............................................................................................................................................................ 333 30.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 365 31.0 Development Support............................................................................................................................................................... 367 32.0 Packaging Information.............................................................................................................................................................. 371 Appendix A: Revision History............................................................................................................................................................. 387 Appendix B: Device Differences ........................................................................................................................................................ 387 Index .................................................................................................................................................................................................. 389 The Microchip Web Site ..................................................................................................................................................................... 395 Customer Change Notification Service .............................................................................................................................................. 395 Customer Support .............................................................................................................................................................................. 395 Reader Response .............................................................................................................................................................................. 396 Product Identification System ............................................................................................................................................................ 397
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 9
PIC12F/LF1822/16F/LF1823
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
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DS41413A-page 10
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
1.0 DEVICE OVERVIEW
The PIC12F/LF1822/16F/LF1823 are described within this data sheet. They are available in 8/14 pin packages. Figure 1-1 shows a block diagram of the PIC12F/LF1822/16F/LF1823 devices. Tables 1-2 and 1-3 show the pinout descriptions. Reference Table 1-1 for peripherals available per device.
TABLE 1-1:
DEVICE PERIPHERAL SUMMARY
PIC12F/LF1822 PIC16F/LF1823
Peripheral
ADC Capacitive Sensing Module (CSM) Data EEPROM Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) SR Latch Capture/Compare/PWM Modules ECCP1 Comparators C1 C2 Master Synchronous Serial Ports MSSP Timers Timer0 Timer1

2010 Microchip Technology Inc.
Preliminary
DS41413A-page 11
PIC12F/LF1822/16F/LF1823
FIGURE 1-1: PIC12F/LF1822/16F/LF1823 BLOCK DIAGRAM
Program Flash Memory CLKR RAM Clock Reference EEPROM
OSC2/CLKO
Timing Generation INTRC Oscillator CPU (Figure 2-1) MCLR PORTA
OSC1/CLKI
PORTC(3)
SR Latch
Timer0
Timer1
ADC 10-Bit
DAC
Comparators
ECCP1
MSSP
Modulator
EUSART
FVR
CapSense
Note
1: 2: 3:
See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. PIC16F/LF1823 only.
DS41413A-page 12
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 1-2: PIC12F/LF1822 PINOUT DESCRIPTION
Function RA0 AN0 CPS0 C1IN+ DACOUT TX CK SDO SS P1B MDOUT ICSPDAT RA1/AN1/CPS1/VREF/C1IN0-/ SRI/RX(1)/DT(1)/SCL/SCK/ MDMIN/ICSPCLK/ICDCLK RA1 AN1 CPS1 VREF C1IN0SRI RX DT SCL SCK MDMIN ICSPCLK RA2/AN2/CPS2/C1OUT/SRQ/ T0CKI/CCP1(1)/P1A(1)/FLT0/SD A/SDI/INT/MDCIN1 RA2 AN2 CPS2 C1OUT SRQ T0CKI CCP1 P1A FLT0 SDA SDI INT MDCIN1 RA3/SS(1)/T1G(1)/VPP/MCLR RA3 SS T1G VPP MCLR Input Type TTL AN AN AN -- -- ST -- ST -- -- ST TTL AN AN AN AN ST ST ST I2CTM ST -- ST TTL AN AN -- -- ST ST -- ST I2CTM CMOS ST ST TTL ST ST HV ST Output Type CMOS General purpose I/O. -- -- -- AN A/D Channel 0 input. Capacitive sensing input 0. Comparator C1 positive input. Digital-to-Analog Converter output. Description
Name RA0/AN0/CPS0/C1IN+/ DACOUT/TX(1)/CK(1)/SDO(1)/ SS(1)/P1B(1)/MDOUT/ICSPDAT/ ICDDAT
CMOS USART asynchronous transmit. CMOS USART synchronous clock. CMOS SPI data output. -- Slave Select input. CMOS PWM output. CMOS Modulator output. CMOS ICSPTM Data I/O. CMOS General purpose I/O. -- -- -- -- -- -- OD A/D Channel 1 input. Capacitive sensing input 1. A/D and DAC Positive Voltage Reference input. Comparator C1 or C2 negative input. SR Latch input. USART asynchronous input. I2CTM clock.
CMOS USART synchronous data. CMOS SPI clock. CMOS Modulator source input. -- -- -- Serial Programming Clock. A/D Channel 2 input. Capacitive sensing input 2. CMOS General purpose I/O.
CMOS Comparator C1 output. CMOS SR Latch non-inverting output. -- Timer0 clock input. CMOS Capture/Compare/PWM 1. CMOS PWM output. -- OD -- -- -- -- -- -- -- -- ECCP Auto-Shutdown Fault input. I2CTM data input/output. SPI data input. External interrupt. Modulator Carrier Input 1. General purpose input. Slave Select input. Timer1 Gate input. Programming voltage. Master Clear with internal pull-up.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 13
PIC12F/LF1822/16F/LF1823
TABLE 1-2: PIC12F/LF1822 PINOUT DESCRIPTION (CONTINUED)
Function RA4 AN3 CPS3 OSC2 CLKOUT T1OSO C1IN1CLKR SDO CK TX P1B T1G MDCIN2 RA5/CLKIN/OSC1/T1OSI/ T1CKI/SRNQ/P1A(1)/CCP1(1)/ DT(1)/RX(1) RA5 CLKIN OSC1 T1OSI T1CKI SRNQ P1A CCP1 DT RX VDD VSS VDD VSS Input Type TTL AN AN -- -- XTAL AN -- -- ST -- -- ST ST TTL CMOS XTAL XTAL ST -- -- ST ST ST Power Power Output Type CMOS General purpose I/O. -- -- A/D Channel 3 input. Capacitive sensing input 3. Description Name RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/C1IN1-/CLKR/ SDO(1)/CK(1)/TX(1)/P1B(1)/ T1G(1)/MDCIN2
CMOS Comparator C2 output. CMOS FOSC/4 output. XTAL -- Timer1 oscillator connection. Comparator C1 negative input.
CMOS Clock Reference output. CMOS SPI data output. CMOS USART synchronous clock. CMOS USART asynchronous transmit. CMOS PWM output. -- -- -- -- XTAL -- Timer1 Gate input. Modulator Carrier Input 2. External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). Timer1 oscillator connection. Timer1 clock input.
CMOS General purpose I/O.
CMOS SR Latch inverting output. CMOS PWM output. CMOS Capture/Compare/PWM 1. CMOS USART synchronous data. -- -- -- USART asynchronous input. Positive supply. Ground reference.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).
DS41413A-page 14
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 1-3: PIC16F/LF1823 PINOUT DESCRIPTION
Function RA0 AN0 CPS0 C1IN+ DACOUT TX CK ICSPDAT RA1/AN1/CPS1/C12IN0-/VREF/ SRI/RX(1)/DT(1)/ICSPCLK/ ICDCLK RA1 AN1 CPS1 C12IN0VREF SRI RX DT ICSPCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/FLT0 RA2 AN2 CPS2 T0CKI INT C1OUT SRQ FLT0 RA3/SS(1)/T1G(1)/VPP/MCLR RA3 SS T1G VPP MCLR RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/SDO(1)/ T1G(1) RA4 AN3 CPS3 OSC2 CLKOUT T1OSO CLKR SDO T1G Input Type TTL AN AN AN -- -- ST ST TTL AN AN AN AN ST ST ST ST TTL AN AN ST ST -- -- ST TTL ST ST HV ST TTL AN AN -- -- XTAL -- -- ST Output Type CMOS General purpose I/O. -- -- -- AN A/D Channel 0 input. Capacitive sensing input 0. Comparator C1 positive input. Digital-to-Analog Converter output. Description
Name RA0/AN0/CPS0/C1IN+/ DACOUT/TX(1)/CK(1)/ICSPDAT/ ICDDAT
CMOS USART asynchronous transmit. CMOS USART synchronous clock. CMOS ICSPTM Data I/O. CMOS General purpose I/O. -- -- -- -- -- -- -- -- -- -- -- A/D Channel 1 input. Capacitive sensing input 1. Comparator C1 or C2 negative input. A/D and DAC Positive Voltage Reference input. SR Latch input. USART asynchronous input. Serial Programming Clock. A/D Channel 2 input. Capacitive sensing input 2. Timer0 clock input. External interrupt.
CMOS USART synchronous data. CMOS General purpose I/O.
CMOS Comparator C1 output. CMOS SR Latch non-inverting output. -- -- -- -- -- -- -- -- ECCP Auto-Shutdown Fault input. General purpose input. Slave Select input. Timer1 Gate input. Programming voltage. Master Clear with internal pull-up. A/D Channel 3 input. Capacitive sensing input 3.
CMOS General purpose I/O.
CMOS Comparator C2 output. CMOS FOSC/4 output. XTAL Timer1 oscillator connection. CMOS Clock Reference output. CMOS SPI data output. -- Timer1 Gate input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 15
PIC12F/LF1822/16F/LF1823
TABLE 1-3: PIC16F/LF1823 PINOUT DESCRIPTION (CONTINUED)
Function RA5 CLKIN OSC1 T1OSI T1CKI RC0/AN4/CPS4/C2IN+/SCL/ SCK RC0 AN4 CPS4 C2IN+ SCL SCK RC1/AN5/CPS5/C12IN1-/SDA/ SDI RC1 AN5 CPS5 C12IN1SDA SDI RC2/AN6/CPS6/C12IN2-/P1D/ SDO(1)/MDCIN1 RC2 AN6 CPS6 C12IN2P1D SDO MDCIN1 RC3/AN7/CPS7/C12IN3-/P1C/ SS(1)/MDMIN RC6 AN7 CPS7 C12IN3P1C SS MDMIN RC4/C2OUT/SRNQ/P1B/CK(1)/ TX(1)/MDOUT RC4 C2OUT SRNQ P1B CK TX MDOUT RC5/P1A/CCP1/DT(1)/RX(1)/ MDCIN2 RC5 P1A CCP1 DT RX MDCIN2 Input Type TTL CMOS XTAL XTAL ST TTL AN AN AN I2CTM ST TTL AN AN AN I2CTM CMOS TTL AN AN AN -- -- ST TTL AN AN AN -- ST -- TTL -- -- -- ST -- -- TTL -- ST ST ST ST Output Type CMOS General purpose I/O. -- -- XTAL -- -- -- -- OD External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). Timer1 oscillator connection. Timer1 clock input. A/D Channel 4 input. Capacitive sensing input 4. Comparator C2 positive input. I2CTM clock. Description Name RA5/CLKIN/OSC1/T1OSI/T1CKI
CMOS General purpose I/O.
CMOS SPI clock. CMOS General purpose I/O. -- -- -- OD -- -- -- -- A/D Channel 5 input. Capacitive sensing input 5. Comparator C1 or C2 negative input. I2CTM data input/output. SPI data input. A/D Channel 6 input. Capacitive sensing input 6. Comparator C1 or C2 negative input.
CMOS General purpose I/O.
CMOS PWM output. CMOS SPI data output. -- -- -- -- -- Modulator Carrier Input 1. A/D Channel 6 input. Capacitive sensing input 6. Comparator C1 or C2 negative input. Slave Select input. CMOS General purpose I/O.
CMOS PWM output. CMOS Modulator source input. CMOS General purpose I/O. CMOS Comparator C2 output. CMOS SR Latch inverting output. CMOS PWM output. CMOS USART synchronous clock. CMOS USART asynchronous transmit. CMOS Modulator output. CMOS General purpose I/O. CMOS PWM output. CMOS Capture/Compare/PWM 1. CMOS USART synchronous data. -- -- USART asynchronous input. Modulator Carrier Input 2.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).
DS41413A-page 16
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 1-3: PIC16F/LF1823 PINOUT DESCRIPTION (CONTINUED)
Function VDD VSS Input Type Power Power Output Type -- -- Positive supply. Ground reference. Description Name VDD VSS
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2CTM = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be assigned to one of two pin locations via software. See APFCON register (Register 12-1).
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 17
PIC12F/LF1822/16F/LF1823
NOTES:
DS41413A-page 18
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
2.0 ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. * * * * Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set
2.1
Automatic Interrupt Context Saving
During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 "Automatic Context Saving", for more information.
2.2
16-level Stack with Overflow and Underflow
These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 "Stack" for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 "Indirect Addressing" for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 "Instruction Set Summary" for more details.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 19
PIC12F/LF1822/16F/LF1823
FIGURE 2-1: CORE BLOCK DIAGRAM
15
Configuration 15 Program Counter Flash Program Memory MUX Data Bus 8
16-LevelStack 8 Level Stack (15-bit) (13-bit) Program Memory Read (PMR) Direct Addr 7 5 BSR Reg FSR reg
RAM
Program Bus
14
12 Addr MUX
RAM Addr
Instruction Reg Instruction reg
Indirect Addr 12 12
15
FSR0 Reg FSR reg FSR1 reg FSR Reg 15 8 3 STATUS reg STATUS Reg
Power-up Timer Instruction Decode & Decode and Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
OSC1/CLKIN OSC2/CLKOUT
W Reg
Internal Oscillator Block VDD VSS
DS41413A-page 20
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
3.0 MEMORY ORGANIZATION
There are three types of memory in PIC12F/LF1822/16F/LF1823 devices: Data Memory, Program Memory and Data EEPROM Memory(1). * Program Memory * Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM - Device Memory Maps - Special Function Registers Summary * Data EEPROM memory(1) Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 "Data EEPROM and Flash Program Memory Control". The following features are associated with access and control of program memory and data memory: * PCL and PCLATH * Stack * Indirect Addressing
3.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC12F/LF1822/16F/LF1823 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 3-1 and ).
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) 2,048 Last Program Memory Address 07FFh
PIC12F/LF1822/16F/LF1823
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 21
PIC12F/LF1822/16F/LF1823
FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC12F/LF1822/16F/LF1823
PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15
3.1.1
READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.
3.1.1.1
RETLW Instruction
Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector Interrupt Vector On-chip Program Memory Page 0 Rollover to Page 0 Wraps to Page 0 07FFh 0800h 0000h 0004h 0005h
The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
EXAMPLE 3-1:
constants brw
RETLW INSTRUCTION
;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data
retlw retlw retlw retlw
DATA0 DATA1 DATA2 DATA3
Wraps to Page 0
my_function ;... LOTS OF CODE... movlw DATA_INDEX call constants ;... THE CONSTANT IS IN W
Wraps to Page 0
The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.
Rollover to Page 0
7FFFh
DS41413A-page 22
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
3.1.1.2 Indirect Read with FSR 3.2.1 CORE REGISTERS
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The HIGH directive will set bit<7> if a label points to a location in program memory. The core registers contain the registers that directly affect the basic operation of the PIC12F/LF1822/16F/LF1823. These registers are listed below: * * * * * * * * * * * * INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank.
EXAMPLE 3-2:
ACCESSING PROGRAM MEMORY VIA FSR
constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;... LOTS OF CODE... MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W
3.2
Data Memory Organization
The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): * * * * 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM
The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as `0'. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 "Indirect Addressing" for more information.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 23
PIC12F/LF1822/16F/LF1823
3.2.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains: * the arithmetic status of the ALU * the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 28.0 "Instruction Set Summary"). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.
REGISTER 3-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4
STATUS: STATUS REGISTER
U-0 -- U-0 -- R-1/q TO R-1/q PD R/W-0/u Z R/W-0/u DC(1) R/W-0/u C(1) bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
Unimplemented: Read as `0' TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Digit Borrow bit(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/Borrow bit(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand.
bit 3
bit 2
bit 1
bit 0
Note 1:
DS41413A-page 24
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
3.2.2 SPECIAL FUNCTION REGISTER 3.2.5 DEVICE MEMORY MAPS
The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. The memory maps for the device family are as shown in Table 3-2.
TABLE 3-2:
MEMORY MAP TABLES
Banks 0-7 8-15 16-23 24-31 31 Table No. Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7
Device PIC12F/LF1822/16F/LF1823
3.2.3
GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory bank.
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 "Linear Data Memory" for more information.
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all banks.
FIGURE 3-2:
BANKED MEMORY PARTITIONING
Memory Region
7-bit Bank Offset 00h
0Bh 0Ch
Core Registers (12 bytes)
Special Function Registers (20 bytes maximum) 1Fh 20h
General Purpose RAM (80 bytes maximum)
6Fh 70h Common RAM (16 bytes) 7Fh
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 25
TABLE 3-3:
BANK0
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA -- PORTC(1) -- -- PIR1 PIR2 -- -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1
PIC12F/LF1822/PIC16F/LF1823 MEMORY MAP, BANKS 0-7
BANK1
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h 0BFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA -- TRISC(1) -- -- PIE1 PIE2 -- -- OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- General Purpose Register 32 Bytes Unimplemented Read as `0' Accesses 70h - 7Fh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41413A-page 26
PIC12F/LF1822/16F/LF1823
BANK2
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA -- LATC(1) -- -- CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- -- 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
BANK3
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA -- ANSELC(1) -- -- EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK4
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA -- WPUC(1) -- -- SSPBUF SSPADD SSPMASK SSPSTAT SSPCON SSPCON2 SSPCON3 -- -- -- -- -- -- -- -- 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK5
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- -- -- -- -- -- -- -- -- 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h
BANK6
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK7
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- IOCAP IOCAN IOCAF -- -- -- -- -- -- CLKRCON -- MDCON MDSRC MDCARL MDCARH
Preliminary
2010 Microchip Technology Inc.
06Fh 070h
General Purpose Register 96 Bytes
Unimplemented Read as `0' 16Fh 170h Accesses 70h - 7Fh 17Fh 1FFh 1EFh 1F0h
Unimplemented Read as `0' 26Fh 270h Accesses 70h - 7Fh 27Fh
Unimplemented Read as `0' 2EFh 2F0h Accesses 70h - 7Fh 2FFh
Unimplemented Read as `0' 36Fh 370h Accesses 70h - 7Fh 37Fh
Unimplemented Read as `0' 3EFh 3F0h Accesses 70h - 7Fh 3FFh
Unimplemented Read as `0'
0EFh 0F0h
Accesses 70h - 7Fh
07Fh Legend: Note 1:
0FFh
= Unimplemented data memory locations, read as `0' Available only on PIC16F/LF1823.
TABLE 3-4:
BANK 8
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 8-15
BANK 9
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
2010 Microchip Technology Inc.
BANK 10
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK 11
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK 12
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK 13
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK 14
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h
BANK 15
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC12F/LF1822/16F/LF1823
Preliminary
DS41413A-page 27
Unimplemented Read as `0' 46Fh 470h Accesses 70h - 7Fh 47Fh Legend: 4FFh 4EFh 4F0h
Unimplemented Read as `0' 56Fh 570h Accesses 70h - 7Fh 57Fh
Unimplemented Read as `0' 5EFh 5F0h Accesses 70h - 7Fh 5FFh
Unimplemented Read as `0' 66Fh 670h Accesses 70h - 7Fh 67Fh
Unimplemented Read as `0' 6EFh 6F0h Accesses 70h - 7Fh 6FFh
Unimplemented Read as `0' 76Fh 770h Accesses 70h - 7Fh 77Fh
Unimplemented Read as `0' 7EFh 7F0h Accesses 70h - 7Fh 7FFh
Unimplemented Read as `0'
Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
TABLE 3-5:
BANK16
800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 16-23
BANK17
880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h
DS41413A-page 28
PIC12F/LF1822/16F/LF1823
BANK18
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h
BANK19
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h
BANK20
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h
BANK21
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h
BANK22
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h
BANK23
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Preliminary
2010 Microchip Technology Inc.
Unimplemented Read as `0' 86Fh 870h Accesses 70h - 7Fh 87Fh Legend: 8FFh 8EFh 8F0h
Unimplemented Read as `0' 96Fh 970h Accesses 70h - 7Fh 97Fh
Unimplemented Read as `0' 9EFh 9F0h Accesses 70h - 7Fh 9FFh
Unimplemented Read as `0' A6Fh A70h Accesses 70h - 7Fh A7Fh
Unimplemented Read as `0' AEFh AF0h Accesses 70h - 7Fh AFFh
Unimplemented Read as `0' B6Fh B70h Accesses 70h - 7Fh B7Fh
Unimplemented Read as `0' BEFh BF0h Accesses 70h - 7Fh BFFh
Unimplemented Read as `0'
Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
TABLE 3-6:
C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANKS 24-31
BANK 25
C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h
2010 Microchip Technology Inc.
BANK 24
BANK 26
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h
BANK 27
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h
BANK 28
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h
BANK 29
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h
BANK 30
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
BANK 31
F80h INDF0 F81h INDF1 F82h PCL F83h STATUS F84h FSR0L F85h FSR0H F86h FSR1L F87h FSR1H F88h BSR F89h WREG F8Ah PCLATH F8Bh INTCON F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-7 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h
PIC12F/LF1822/16F/LF1823
Preliminary
DS41413A-page 29
Unimplemented Read as `0' C6Fh C70h Accesses 70h - 7Fh CFFh Legend: CFFh CEFh CF0h
Unimplemented Read as `0' D6Fh D70h Accesses 70h - 7Fh D7Fh
Unimplemented Read as `0' DEFh DF0h Accesses 70h - 7Fh DFFh
Unimplemented Read as `0' E6Fh E70h Accesses 70h - 7Fh E7Fh
Unimplemented Read as `0' EEFh EF0h Accesses 70h - 7Fh EFFh
Unimplemented Read as `0' F6Fh F70h Accesses 70h - 7Fh F7Fh
Unimplemented Read as `0' FEFh FF0h Accesses 70h - 7Fh FFFh Accesses 70h - 7Fh
= Unimplemented data memory locations, read as `0'
PIC12F/LF1822/16F/LF1823
TABLE 3-7: PIC12F/LF1822/16F/LF1823 MEMORY MAP, BANK 31
Bank 31
FA0h Unimplemented Read as `0' FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend:
3.2.6
SPECIAL FUNCTION REGISTERS SUMMARY
The Special Function Register Summary for the device family are as follows:
Device Bank(s) 0 1 2 3 4 PIC12F/LF1822/16F/LF1823 5 6 7 8 9-30 31 Page No. 31 32 33 34 35 36 37 38 39 40 41
STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD -- STKPTR TOSL TOSH = Unimplemented data memory locations, read as `0'.
DS41413A-page 30
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 0 000h(1) 001h(1) 002h(1) 003h(1) 004h(1) 005h(1) 006h(1) 007h(1) 008h(1) 009h(1) 00Ah(1) 00Bh(1) 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA -- PORTC(2) -- -- PIR1 PIR2 -- -- TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON -- CPSCON0 CPSCON1 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- Unimplemented -- Unimplemented Unimplemented TMR1GIF OSFIF Unimplemented Unimplemented Timer0 Module Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS1 TMR1GE TMR1CS0 T1GPOL T1CKPS<1:0> T1GTM T1GSPM T1OSCEN T1GGO/ DONE T1SYNC T1GVAL -- TMR1ON T1GSS<1:0> ADIF C2IF(2) RCIF C1IF TXIF EEIF SSP1IF BCL1IF CCP1IF -- TMR2IF -- TMR1IF -- -- RC5 RC4 RC3 RC2 RC1 RC0 Write Buffer for the upper 7 bits of the Program Counter PEIE -- TMR0IE RA5 INTE RA4 IOCIE RA3 TMR0IF RA2 INTF RA1 IOCIF RA0 -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u --xx xxxx --xx xxxx -- -- -- -- -- -- --xx xxxx --xx xxxx Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
0000 0000 0000 0000 0000 0--- 0000 0---- -- -- --
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS<3:0> TMR2ON CPSRNG<1:0> CPSCH<3:2>(2) T2CKPS<1:0> CPSOUT T0XCS -000 0000 -000 0000 -- -- 00-- 0000 00-- 0000 ---- 0000 ---- 0000
Timer2 Module Register Timer2 Period Register -- Unimplemented CPSON -- CPSRM -- -- -- -- -- CPSCH<1:0>
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 31
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 1 080h(1) 081h(1) 082h(1) 083h(1) 084h(1) 085h(1) 086h(1) 087h(1) 088h(1) 089h(1) 08Ah(1) 08Bh(1) 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA -- TRISC(2) -- -- PIE1 PIE2 -- -- OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- Unimplemented -- Unimplemented Unimplemented TMR1GIE OSFIE Unimplemented Unimplemented WPUEN STKOVF -- -- SPLLEN T1OSCR PLLR A/D Result Register Low A/D Result Register High -- ADFM Unimplemented ADCS<2:0> CHS<4:0> -- -- GO/DONE ADON ADPREF<1:0> INTEDG STKUNF -- -- IRCF<3:0> OSTS HFIOFR HFIOFL TMR0CS -- TMR0SE -- PSA RMCLR WDTPS<4:0> TUN<5:0> -- MFIOFR SCS<1:0> LFIOFR HFIOFS RI PS<2:0> POR BOR ADIE C2IE(2) RCIE C1IE TXIE EEIE SSP1IE BCL1IE CCP1IE -- TMR2IE -- TMR1IE -- -- TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 Write Buffer for the upper 7 bits of the Program Counter PEIE -- TMR0IE TRISA5 INTE TRISA4 IOCIE TRISA3 TMR0IF TRISA2 INTF TRISA1 IOCIF TRISA0 -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u --11 1111 --11 1111 -- -- -- -- -- -- --11 1111 --11 1111 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
0000 0000 0000 0000 0000 0--- 0000 0---- -- -- --
1111 1111 1111 1111 00-- 11qq qq-- qquu --00 0000 --00 0000 0011 1-00 0011 1-00 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -000 0000 -000 0000 0000 --00 0000 --00 -- -- SWDTEN --01 0110 --01 0110
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
DS41413A-page 32
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 2 100h(1) 101h(1) 102h(1) 103h(1) 104h(1) 105h(1) 106h(1) 107h(1) 108h(1) 109h(1) 10Ah(1) 10Bh(1) 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA -- LATC(2) -- -- CM1CON0 CM1CON1 CM2CON0 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 -- APFCON -- --
(2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
Name
Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- Unimplemented -- Unimplemented Unimplemented C1ON C1INTP C2ON C2INTP -- SBOREN FVREN DACEN --SRLEN SRSPE SRSCKE C1OUT C1INTN C2OUT C2INTN -- -- FVRRDY DACLPS --C1OE C2OE -- -- Reserved DACOE --SRCLK<2:0> SRSC2E(2) SRSC1E SRQEN SRRPE C1POL C2POL -- -- Reserved ---- -- -- -- -- -- C1SP -- C2SP -- -- -- C1HYS C1NCH1(2) C2HYS C1SYNC C1NCH0 C2SYNC C1PCH<1:0> C2PCH<1:0> -- LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 Write Buffer for the upper 7 bits of the Program Counter PEIE -- TMR0IE LATA5 INTE LATA4 IOCIE -- TMR0IF LATA2 INTF LATA1 IOCIF LATA0 -- -- BSR<4:0>
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u --xx -xxx --uu -uuu -- -- -- -- -- -- --xx xxxx --uu uuuu
0000 -100 0000 -100 0000 ---0 0000 ---0 0000 -100 0000 -100 0000 --00 0000 --00 ---- --00 ---- --00 0qrr 0000 0qrr 0000 000- 00-- 000- 00----0 0000 ---0 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- --
CM2CON1(2)
C2NCH<1:0> MC2OUT(2) MC1OUT -- --SRPS SRRC2E
(2)
BORRDY 1--- ---q u--- ---u --SRPR SRRC1E
CDAFVR<1:0> DACPSS<1:0> DACR<4:0> SRNQEN SRRCKE
ADFVR<1:0>
Unimplemented RXDTSEL SDOSEL SSSEL --T1GSEL TXCKSEL P1BSEL Unimplemented Unimplemented
CCP1SEL 000- 0000 000- 0000 -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 33
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 3 180h(1) 181h(1) 182h(1) 183h(1) 184h(1) 185h(1) 186h(1) 187h(1) 188h(1) 189h(1) 18Ah(1) 18Bh(1) 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA -- ANSELC(2) -- -- EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 -- -- RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- Unimplemented -- Unimplemented Unimplemented EEPROM / Program Memory Address Register Low Byte -- -- EEPGD Unimplemented Unimplemented USART Receive Data Register USART Transmit Data Register Baud Rate Generator Data Register Low Baud Rate Generator Data Register High SPEN CSRC ABDOVF RX9 TX9 RCIDL SREN TXEN -- CREN SYNC SCKP ADDEN SENDB BRG16 FERR BRGH -- OERR TRMT WUE RX9D TX9D ABDEN EEPROM / Program Memory Address Register High Byte -- CFGS EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD EEPROM / Program Memory Read Data Register Low Byte -- -- -- ANSC3 ANSC2 ANSC1 ANSC0 Write Buffer for the upper 7 bits of the Program Counter PEIE -- TMR0IE -- INTE ANSA4 IOCIE -- TMR0IF ANSA2 INTF ANSA1 IOCIF ANSA0 -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u ---1 -111 ---1 -111 -- -- -- -- -- -- ---- 1111 ---- 1111 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu 0000 x000 0000 q000 0000 0000 0000 0000 -- -- -- --
EEPROM control register 2
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
DS41413A-page 34
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 4 200h(1) 201h(1) 202h(1) 203h(1) 204h(1) 205h(1) 206h(1) 207h(1) 208h(1) 209h(1) 20Ah(1) 20Bh(1) 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA -- WPUC(2) -- -- SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 -- -- -- -- -- -- -- -- SMP WCOL GCEN ACKTIM Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CKE SSPOV ACKSTAT PCIE D/A SSPEN ACKDT SCIE Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE -- Unimplemented -- Unimplemented Unimplemented Synchronous Serial Port Receive Buffer/Transmit Register ADD<7:0> MSK<7:0> P CKP ACKEN BOEN RCEN SDAHT S R/W PEN SBCDE UA RSEN AHEN BF SEN DHEN SSPM<3:0> -- WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 Write Buffer for the upper 7 bits of the Program Counter PEIE -- TMR0IE WPUA5 INTE WPUA4 IOCIE WPUA3 TMR0IF WPUA2 INTF WPUA1 IOCIF WPUA0 -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u --11 1111 --11 1111 -- -- -- -- -- -- --11 1111 --11 1111 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
xxxx xxxx uuuu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 35
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 5 280h(1) 281h(1) 282h(1) 283h(1) 284h(1) 285h(1) 286h(1) 287h(1) 288h(1) 289h(1) 28Ah(1) 28Bh(1) 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) P1M<1:0> P1RSEN CCP1ASE -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- CCP1AS<2:0> -- STR1SYNC DC1B<1:0> P1DC<6:0> PSS1AC<1:0> STR1D STR1C PSS1BD<1:0> STR1B STR1A CCP1M<3:0> Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---0 0001 ---0 0001 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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Preliminary
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PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 6 300h(1) 301h(1) 302h(1) 303h(1) 304h(1) 305h(1) 306h(1) 307h(1) 308h(1) 309h(1) 30Ah(1) 30Bh(1) 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 37
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 7 380h(1) 381h(1) 382h(1) 383h(1) 384h(1) 385h(1) 386h(1) 387h(1) 388h(1) 389h(1) 38Ah(1) 38Bh(1) 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- IOCAP IOCAN IOCAF -- -- -- -- -- -- CLKRCON -- MDCON MDSRC MDCARL MDCARH Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CLKREN MDEN MDMSODIS MDCLODIS MDCHODIS CLKROE MDOE -- MDCLPOL CLKRSLR MDSLR -- MDCLSYNC CLKRDC<1:0> MDOPOL -- -- -- MDOUT -- CLKRDIV<2:0> -- MDBIT Unimplemented MDMS<3:0> MDCL<3:0> MDCH<3:0> -- -- -- IOCAP5 IOCAN5 IOCAF5 IOCAP4 IOCAN4 IOCAF4 IOCAP3 IOCAN3 IOCAF3 IOCAP2 IOCAN2 IOCAF2 IOCAP1 IOCAN1 IOCAF1 IOCAP0 IOCAN0 IOCAF0 Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
--00 0000 --00 0000 --00 0000 --00 0000 --00 0000 --00 0000 -- -- -- -- -- -- -- -- -- -- -- -- -- --
0011 0000 0011 0000 0010 ---0 0010 ---0 x--- xxxx u--- uuuu xxx- xxxx uuu- uuuu xxx- xxxx uuu- uuuu
MDCHPOL MDCHSYNC
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 8 400h(1) 401h(1) 402h(1) 403h(1) 404h(1) 405h(1) 406h(1) 407h(1) 408h(1) 409h(1) 40Ah(1) 40Bh(1) 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 39
PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Banks 9-30 x00h/ x80h(1) x00h/ x81h(1) x02h/ x82h(1) x03h/ x83h(1) x04h/ x84h(1) x05h/ x85h(1) x06h/ x86h(1) x07h/ x87h(1) x08h/ x88h(1) x09h/ x89h(1) x0Ah/ x8Ah(1) x0Bh/ x8Bh(1) x0Ch/ x8Ch -- x1Fh/ x9Fh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR<4:0> ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 000x 0000 000u -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -- --
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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Preliminary
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PIC12F/LF1822/16F/LF1823
TABLE 3-8:
Address Bank 31 F80h(1) F81h(1) F82h(1) F83h(1) F84h(1) F85h(1) F86h(1) F87h(1) F88h(1) F89h(1) F8Ah(1) F8Bh(1) F8Ch -- FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Note INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON -- Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte -- -- -- TO PD Z DC C Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer -- Working Register -- GIE Unimplemented Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF -- -- BSR<4:0> xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 ---1 1000 ---q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u -- -- Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets
STATUS_ SHAD WREG_ SHAD BSR_ SHAD PCLATH_ SHAD FSR0L_ SHAD FSR0H_ SHAD FSR1L_ SHAD FSR1H_ SHAD -- STKPTR TOSL TOSH
--
--
--
--
--
Z
DC
C
---- -xxx ---- -uuu 0000 0000 uuuu uuuu
Working Register Shadow -- -- -- -- Bank Select Register Shadow
---x xxxx ---u uuuu -xxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- --
Program Counter Latch High Register Shadow
Indirect Data Memory Address 0 Low Pointer Shadow Indirect Data Memory Address 0 High Pointer Shadow Indirect Data Memory Address 1 Low Pointer Shadow Indirect Data Memory Address 1 High Pointer Shadow Unimplemented -- -- -- Current Stack pointer Top-of-Stack Low byte -- Top-of-Stack High byte
---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as `0'. 1: These registers can be addressed from any bank. 2: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 41
PIC12F/LF1822/16F/LF1823
3.3 PCL and PCLATH
3.3.3 COMPUTED FUNCTION CALLS
The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH.
FIGURE 3-3:
14 PCH
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 0
Instruction with PCL as Destination
PC
6 PCLATH 14
7
0
8
ALU Result PCL 0
GOTO, CALL
PC
PCH
3.3.4
BRANCHING
PCLATH PC
6 14
4
0
11
OPCODE <10:0> PCH PCL 0
CALLW
PCLATH
6
7
0
8
W PCL 0
The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction.
PC
14
PCH
BRW
PC + W 14 PCH PCL 0
BRA
15
PC
PC + OPCODE <8:0>
15
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, "Implementing a Table Read" (DS00556).
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Preliminary
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PIC12F/LF1822/16F/LF1823
3.4 Stack
3.4.1 ACCESSING THE STACK
All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through and 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit = 0 (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow. Note: Care should be taken when modifying the STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement STKPTR. Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack.
FIGURE 3-4:
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
STKPTR = 0x1F
Stack Reset Disabled (STVREN = 0)
Initial Stack Configuration: After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return `0'. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
Stack Reset Enabled (STVREN = 1)
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Preliminary
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PIC12F/LF1822/16F/LF1823
FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00 Return Address
STKPTR = 0x00
This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 3
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Return Address Return Address Return Address Return Address Return Address Return Address Return Address
STKPTR = 0x06
After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack.
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PIC12F/LF1822/16F/LF1823
FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL 0x00
Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address
STKPTR = 0x10
When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten.
3.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is set to `1', the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return `0' and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: * Traditional Data Memory * Linear Data Memory * Program Flash Memory
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Preliminary
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PIC12F/LF1822/16F/LF1823
FIGURE 3-8: INDIRECT ADDRESSING
0x0000 0x0000 Traditional Data Memory
0x0FFF 0x1000 0x1FFF 0x2000
0x0FFF Reserved
Linear Data Memory
0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000
Program Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
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PIC12F/LF1822/16F/LF1823
3.5.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
FIGURE 3-9:
TRADITIONAL DATA MEMORY MAP
Direct Addressing Indirect Addressing 0 7 0 0 0 FSRxH 0 Bank Select 1111 Location Select 0 7 FSRxL 0
4
BSR
0
6
From Opcode
Bank Select
Location Select 0x00 0000 0001 0010
0x7F Bank 0 Bank 1 Bank 2 Bank 31
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Preliminary
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PIC12F/LF1822/16F/LF1823
3.5.2 LINEAR DATA MEMORY 3.5.3 PROGRAM FLASH MEMORY
The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete.
FIGURE 3-10:
LINEAR DATA MEMORY MAP
0 7 FSRnL 0
FIGURE 3-11:
7 1
PROGRAM FLASH MEMORY MAP
0 7 FSRnL 0
FSRnH
7 FSRnH 001
Location Select Location Select 0x2000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F
0x8000
0x0000
Program Flash Memory (low 8 bits)
0xF20 Bank 30 0x29AF 0xF6F 0xFFFF 0x7FFF
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PIC12F/LF1822/16F/LF1823
4.0 DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h.
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Preliminary
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PIC12F/LF1822/16F/LF1823
REGISTER 4-1:
R/P-1/1 FCMEN bit 13 R/P-1/1 MCLRE bit 6 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled CLKOUTEN: Clock Out Enable bit If FOSC configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: RA3/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register. PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit R/P-1/1 PWRTE R/P-1/1 WDTE1 R/P-1/1 WDTE0 R/P-1/1 FOSC2 R/P-1/1 FOSC1 R/P-1/1 FOSC0 bit 0
CONFIGURATION WORD 1
R/P-1/1 IESO R/P-1/1 CLKOUTEN R/P-1/1 BOREN1 R/P-1/1 BOREN0 R/P-1/1 CPD R/P-1/1 CP bit 7
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1: 2: 3:
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REGISTER 4-1:
bit 2-0
CONFIGURATION WORD 1 (CONTINUED)
FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off.
Note 1: 2: 3:
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REGISTER 4-2:
R/P-1/1 LVP bit 13 U-1 -- bit 6 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 13 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit U-1 -- R-1 U-1 -- U-1 -- R/P-1/1 WRT1 R/P-1/1 WRT0 bit 0
CONFIGURATION WORD 2
R/P-1/1 DEBUG U-1 -- R/P-1/1 BORV R/P-1/1 STVREN R/P-1/1 PLLEN U-1 -- bit 7
Reserved
LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger Unimplemented: Read as `1' BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V (typical) 0 = Brown-out Reset voltage set to 2.5V (typical) STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled Unimplemented: Read as `1' Reserved: This location should be programmed to a `1'. Unimplemented: Read as `1' WRT<1:0>: Flash Memory Self-Write Protection bits 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP.
bit 12
bit 11 bit 10
bit 9
bit 8
bit 7-5 bit 4 bit 3-2 bit 1-0
Note 1:
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4.2 Code Protection
Code protection allows the device to be protected from unauthorized access. Program memory protection and data EEPROM protection are controlled independently. Internal access to the program memory and data EEPROM are unaffected by any code protection setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.3 "Write Protection" for more information.
4.2.2
DATA EEPROM PROTECTION
The entire data EEPROM is protected from external reads and writes by the CPD bit. When CPD = 0, external reads and writes of data EEPROM are inhibited. The CPU can continue to read and write data EEPROM regardless of the protection bit settings.
4.3
Write Protection
Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC16F/LF1826/27/PIC12F/LF1822 Memory Programming Specification" (DS41390).
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4.5 Device ID and Revision ID
The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 11.5 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
REGISTER 4-3:
R DEV8 bit 13 R DEV1 bit 6 Legend: R = Readable bit -n = Value at POR bit 13-5
DEVICEID: DEVICE ID REGISTER(1)
R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 bit 7 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 U = Unimplemented bit, read as `0' W = Writable bit `1' = Bit is set `0' = Bit is cleared x = Bit is unknown
DEV<8:0>: Device ID bits 100111100 = PIC12F1822 100111101 = PIC16F1823 101000100 = PIC12LF1822 101000101 = PIC16LF1823 REV<4:0>: Revision ID bits These bits are used to identify the revision.
bit 4-0
Note 1:
This location cannot be written.
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5.0
5.1
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
The oscillator module can be configured in one of six clock modes. 1. 2. 3. 4. 5. 6. EC - External clock (ECL, ECM, ECH. See Section 5.2.1.1 "EC Mode"). LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode. HS - High Gain Crystal or Ceramic Resonator mode. RC - External Resistor-Capacitor (RC). INTOSC - Internal oscillator.
The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, EC or RC modes) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources
Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Word 1. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The EC clock mode relies on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The RC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high frequency clock sources, designated LFINTOSC, MFINTOSC, and HFINTOSC. (see Internal Oscillator Block, Figure 5-1). A wide selection of device clock frequencies may be derived from these three clock sources.
FIGURE 5-1:
SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM
External Oscillator
OSC2 Sleep OSC1 Oscillator Timer1 T1OSO T1OSCEN Enable Oscillator FOSC<2:0> = 100 4 x PLL
LP, XT, HS, RC, EC
Sleep MUX T1OSC CPU and Peripherals
T1OSI
IRCF<3:0> 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz
Internal Oscillator
Internal Oscillator Block HFPLL 500 kHz Source 31 kHz Source Postscaler 16 MHz (HFINTOSC) 500 kHz (MFINTOSC)
MUX
Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules
31 kHz (LFINTOSC)
WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules
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5.2 Clock Source Types
Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated phase-locked-loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHZ (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 5.3 "Clock Switching" for additional information. The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed.
FIGURE 5-2:
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC(R) MCU OSC2/CLKOUT
Clock from Ext. System
FOSC/4 or I/O(1) Note 1:
Output depends upon CLKOUTEN bit of the Configuration Word 1.
5.2.1
EXTERNAL CLOCK SOURCES 5.2.1.2 LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 5-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively.
An external clock source can be used as the device system clock by performing one of the following actions: * Program the FOSC<2:0> bits in the Configuration Word 1 to select an external clock source that will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Timer1 Oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 5.3 "Clock Switching"for more information.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 5-2 shows the pin connections for EC mode. EC mode has 3 power modes to select from through Configuration Word 1: * High-power, 4-32 MHz (FOSC = 111) * Medium power, 0.5-4 MHz (FOSC = 110) * Low-power, 0-0.5 MHz (FOSC = 101)
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FIGURE 5-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN C1 Quartz Crystal RF(2) To Internal Logic Sleep C1
FIGURE 5-4:
CERAMIC RESONATOR OPERATION (XT OR HS MODE)
PIC(R) MCU
OSC1/CLKIN To Internal Logic RP(3) RF(2) Sleep
C2
RS(1)
OSC2/CLKOUT
C2 Ceramic RS(1) Resonator
OSC2/CLKOUT
Note 1: 2:
A series resistor (RS) may be required for quartz crystals with low drive level. The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
Note 1:
A series resistor (RS) may be required for ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation.
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949)
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 5.4 "Two-Speed Clock Start-up Mode").
5.2.1.4
4X PLL
The oscillator module contains a 4X PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4X PLL must fall within specifications. See the PLL Clock Timing Specifications in Section 29.0 "Electrical Specifications". The 4X PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Word 2 to a `1'. Write the SPLLEN bit in the OSCCON register to a `1'. If the PLLEN bit in Configuration Word 2 is programmed to a `1', then the value of SPLLEN is ignored.
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5.2.1.5 TIMER1 Oscillator 5.2.1.6 External RC Mode
The Timer1 Oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The Timer1 Oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 5.3 "Clock Switching" for more information. The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. Figure 5-6 shows the external RC mode connections.
FIGURE 5-5:
QUARTZ CRYSTAL OPERATION (TIMER1 OSCILLATOR)
PIC(R)
T1OSI
FIGURE 5-6:
VDD
EXTERNAL RC MODES
PIC(R) MCU
MCU
REXT OSC1/CLKIN
To Internal Logic
C1 32.768 kHz Quartz Crystal
Internal Clock
CEXT VSS FOSC/4 or I/O(1) OSC2/CLKOUT
C2
T1OSO
Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V
Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Applications Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288)
Note 1:
Output depends upon CLKOUTEN bit of the Configuration Word 1.
The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: * threshold voltage variation * component tolerances * packaging variations in capacitance The user also needs to take into account variation due to tolerance of external RC components used.
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5.2.2 INTERNAL CLOCK SOURCES 5.2.2.1 HFINTOSC
The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: * Program the FOSC<2:0> bits in Configuration Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 5.3 "Clock Switching"for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1. The internal oscillator block has two independent oscillators and a dedicated Phase-Locked Loop, HFPLL that can produce one of three internal system clock sources. 1. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Locked Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 5-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The HFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x'. The High Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running and can be utilized. The High Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.
5.2.2.2
MFINTOSC
2.
The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The MFINTOSC is enabled by: * Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized.
3.
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5.2.2.3 Internal Oscillator Frequency Adjustment 5.2.2.5 Internal Oscillator Frequency Selection
The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 5-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is `0'. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The output of the 16 MHz HFINTOSC and 31 kHz LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: * * * * * * * * * * * * 32 MHz (requires 4X PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (Default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to `0111' and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency.
5.2.2.4
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 5-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 5.2.2.7 "Internal Oscillator Clock Switch Timing" for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: * Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and * FOSC<2:0> = 100, or * Set the System Clock Source (SCS) bits of the OSCCON register to `1x' Peripherals that use the LFINTOSC are: * Power-up Timer (PWRT) * Watchdog Timer (WDT) * Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized.
The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.
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PIC12F/LF1822/16F/LF1823
5.2.2.6 32 MHz Internal Oscillator Frequency Selection 5.2.2.7 Internal Oscillator Clock Switch Timing
The Internal Oscillator Block can be used with the 4X PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: * The FOSC bits in Configuration Word 1 must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100). * The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC selection (IRCF<3:0> = 1110). * The SPLLEN bit in the OSCCON register must be set to enable the 4xPLL, or the PLLEN bit of the Configuration Word 2 must be programmed to a `1'. Note: When using the PLLEN bit of the Configuration Word 2, the 4xPLL cannot be disabled by software and the 8 MHz HFINTOSC option will no longer be available. When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 5-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete.
The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to `1x'. The SCS bits must be set to `00' to use the 4xPLL with the internal oscilator.
5. 6. 7.
See Figure 5-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Section 29.0 "Electrical Specifications".
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FIGURE 5-7: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock
LFINTOSC (FSCM and WDT disabled)
Start-up Time
2-cycle Sync
Running
0
0
HFINTOSC/ MFINTOSC HFINTOSC/ MFINTOSC LFINTOSC IRCF <3:0> System Clock
LFINTOSC (Either FSCM or WDT enabled)
2-cycle Sync
Running
0
0
LFINTOSC LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Start-up Time
2-cycle Sync
Running
HFINTOSC/ MFINTOSC IRCF <3:0> System Clock
=0
0
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5.3 Clock Switching
5.3.3 TIMER1 OSCILLATOR
The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: * Default system oscillator determined by FOSC bits in Configuration Word 1 * Timer1 32 kHz crystal oscillator * Internal Oscillator Block (INTOSC) The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSO and T1OSI device pins. The Timer1 oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 20.0 "Timer1 Module with Gate Control" for more information about the Timer1 peripheral.
5.3.1
SYSTEM CLOCK SELECT (SCS) BITS
5.3.4
TIMER1 OSCILLATOR READY (T1OSCR) BIT
The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals. * When the SCS bits of the OSCCON register = 00, the system clock source is determined by value of the FOSC<2:0> bits in the Configuration Word 1. * When the SCS bits of the OSCCON register = 01, the system clock source is the Timer1 oscillator. * When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source.
The user must ensure that the Timer1 Oscillator is ready to be used before it is selected as a system clock source. The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator.
When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIME-OUT STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the Timer1 Oscillator.
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5.4 Two-Speed Clock Start-up Mode
5.4.1
Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear.
TWO-SPEED START-UP MODE CONFIGURATION
Two-Speed Start-up mode is configured by the following settings: * IESO (of the Configuration Word 1) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). * SCS (of the OSCCON register) = 00. * FOSC<2:0> bits in the Configuration Word 1 configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: * Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or * Wake-up from Sleep.
TABLE 5-1:
Switch From Sleep/POR Sleep/POR LFINTOSC Sleep/POR Any clock source Any clock source Any clock source PLL inactive Note 1:
OSCILLATOR SWITCHING DELAYS
Switch To LFINTOSC(1) MFINTOSC(1) HFINTOSC(1) RC(1) Frequency 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz DC - 32 MHz DC - 32 MHz 32 kHz-20 MHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 31 kHz 32 kHz 16-32 MHz Oscillator Delay Oscillator Warm-up Delay (TWARM) 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST) 2 ms (approx.)
EC, RC(1) EC, Timer1 Oscillator LP, XT, HS(1) MFINTOSC(1) HFINTOSC(1) LFINTOSC(1) Timer1 Oscillator PLL active
PLL inactive.
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5.4.2
1. 2.
TWO-SPEED START-UP SEQUENCE
5.4.3
CHECKING TWO-SPEED CLOCK STATUS
3. 4. 5. 6. 7.
Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source.
Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator.
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC T TOST OSC1 0 1 1022 1023
OSC2 Program Counter PC - N PC PC + 1
System Clock
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5.5 Fail-Safe Clock Monitor
5.5.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word 1. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Timer1 Oscillator and RC). The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device will be operating from the external clock source. The Fail-Safe condition must be cleared before the OSFIF flag can be cleared.
FIGURE 5-9:
FSCM BLOCK DIAGRAM
Clock Monitor Latch S Q
5.5.4
RESET OR WAKE-UP FROM SLEEP
External Clock
LFINTOSC Oscillator 31 kHz (~32 s)
/ 64 488 Hz (~2 ms)
R
Q
The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating.
Clock Failure Detected
Sample Clock
Note:
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 5-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low.
Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed.
5.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs.
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FIGURE 5-10:
Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Failure Detected
Test Note:
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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PIC12F/LF1822/16F/LF1823
5.6 Oscillator Control Registers
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 -- R/W-0/0 R/W-0/0 bit 0 IRCF<3:0> SCS<1:0>
REGISTER 5-1:
R/W-0/0 SPLLEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SPLLEN: Software PLL Enable bit If PLLEN in Configuration Word 1 = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Word 1 = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits 000x = 31 kHz LF 0010 = 31.25 kHz MF 0011 = 31.25 kHz HF(1) 0100 = 62.5 kHz MF 0101 = 125 kHz MF 0110 = 250 kHz MF 0111 = 500 kHz MF (default upon Reset) 1000 = 125 kHz HF(1) 1001 = 250 kHz HF(1) 1010 = 500 kHz HF(1) 1011 = 1 MHz HF 1100 = 2 MHz HF 1101 = 4 MHz HF 1110 = 8 MHz or 32 MHz HF(see Section 5.2.2.1 "HFINTOSC") 1111 = 16 MHz HF Unimplemented: Read as `0' SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1 Duplicate frequency derived from HFINTOSC.
bit 2 bit 1-0
Note 1:
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REGISTER 5-2:
R-1/q T1OSCR bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer1 oscillator is not ready If T1OSCEN = 0: 1 = Timer1 clock source is always ready PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready OSTS: Oscillator Start-up Time-out Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1 0 = Running from an internal oscillator (FOSC<2:0> = 100) HFIOFR: High Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready HFIOFL: High Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate MFIOFR: Medium Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Conditional
OSCSTAT: OSCILLATOR STATUS REGISTER
R-0/q PLLR R-q/q OSTS R-0/q HFIOFR R-0/q HFIOFL R-q/q MFIOFR R-0/0 LFIOFR R-0/q HFIOFS bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 5-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = * * * 000001 = 000000 = Oscillator module is running at the factory-calibrated frequency 111111 = * * * 100000 = Minimum frequency U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 TUN<5:0>
TABLE 5-2:
Name OSCCON OSCSTAT OSCTUNE PIE2 PIR2 T1CON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7 SPLLEN T1OSCR -- OSFIE OSFIF PLLR -- C2IE(1) C2IF
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2 --
Bit 1
Bit 0
Register on Page 68 69 70 91 93 180
IRCF<3:0> OSTS C1IE C1IF HFIOFR EEIE EEIF HFIOFL BCL1IE BCL1IF T1OSCEN TUN<5:0>
SCS<1:0> LFIOFR -- -- -- HFIOFS -- -- TMR1ON
MFIOFR -- -- T1SYNC
TMR1CS<1:0>
T1CKPS<1:0>
-- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. PIC16F/LF1823 only.
TABLE 5-3:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO Bit 11/3 CLKOUTEN Bit 10/2 Bit 9/1 Bit 8/0 CPD Register on Page 50
CONFIG1 Legend: Note 1:
BOREN<1:0> FOSC<2:0>
WDTE<1:0>
-- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. PIC12F1822/16F1823 only.
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PIC12F/LF1822/16F/LF1823
6.0 REFERENCE CLOCK MODULE
6.3 Conflicts with the CLKR pin
The reference clock module provides the ability to send a divided clock to the clock output pin of the device (CLKR) and provide a secondary internal clock source to the modulator module. This module is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. The reference clock module includes the following features: * * * * * * System clock is the source Available in all oscillator configurations Programmable clock divider Output enable to a port pin Selectable duty cycle Slew rate control There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: * LP, XT, or HS oscillator mode is selected. * CLKOUT function is enabled. Even if either of these cases are true, the module can still be enabled and the reference clock signal may be used in conjunction with the modulator module.
6.3.1
OSCILLATOR MODES
If LP, XT, or HS oscillator modes are selected, the OSC2/CLKR pin must be used as an oscillator input pin and the CLKR output cannot be enabled. See Section 5.2 "Clock Source Types" for more information on different oscillator modes.
The reference clock module is controlled by the CLKRCON register (Register 6-1) and is enabled when setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set. The CLKRDIV<2:0> bits enable the selection of 8 different clock divider options. The CLKRDC<1:0> bits can be used to modify the duty cycle of the output clock(1). The CLKRSLR bit controls slew rate limiting. Note 1: If the base clock rate is selected without a divider, the output clock will always have a duty cycle equal to that of the source clock, unless a 0% duty cycle is selected. If the clock divider is set to base clock/2, then 25% and 75% duty cycle accuracy will be dependent upon the source clock. For information on using the reference clock output with the modulator module, see Section 22.0 "Data Signal Modulator".
6.3.2
CLKOUT FUNCTION
The CLKOUT function has a higher priority than the reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration Word 1, FOSC/4 will always be output on the port pin. Reference Section 4.0 "Device Configuration" for more information.
6.4
Operation During Sleep
As the reference clock module relies on the system clock as its source, and the system clock is disabled in Sleep, the module does not function in Sleep, even if an external clock source or the Timer1 clock source is configured as the system clock. The module outputs will remain in their current state until the device exits Sleep.
6.1
Slew rate
The slew rate limitation on the output port pin can be disabled. The Slew Rate limitation can be removed by clearing the CLKRSLR bit in the CLKRCON register.
6.2
Effects of a Reset
Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.
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REGISTER 6-1:
R/W-0/0 CLKREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CLKREN: Reference Clock Module Enable bit 1 = Reference clock module is enabled 0 = Reference clock module is disabled CLKROE: Reference Clock Output Enable bit(3) 1 = Reference clock output is enabled on CLKR pin 0 = Reference clock output disabled on CLKR pin CLKRSLR: Reference Clock Slew Rate Control limiting enable bit 1 = Slew rate limiting is enabled 0 = Slew rate limiting is disabled CLKRDC<1:0>: Reference Clock Duty Cycle bits 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% CLKRDIV<2:0> Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2(1) 000 = Base clock value(2) U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0 CLKROE R/W-1/1 CLKRSLR R/W-1/1 CLKRDC1 R/W-0/0 CLKRDC0 R/W-0/0 CLKRDIV2 R/W-0/0 CLKRDIV1 R/W-0/0 CLKRDIV0 bit 0
bit 6
bit 5
bit 4-3
bit 2-0
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0% is selected. 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration Word 1 = 0 will result in FOSC/4. See Section 6.3 "Conflicts with the CLKR pin" for details.
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TABLE 6-1:
Name CLKRCON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES
Bit 7 CLKREN Bit 6 CLKROE Bit 5 CLKRSLR Bit 4 CLKRDC1 Bit 3 CLKRDC0 Bit 2 CLKRDIV2 Bit 1 Bit 0 Register on Page 72
CLKRDIV1 CLKRDIV0
-- = unimplemented locations read as `0'. Shaded cells are not used by reference clock sources.
TABLE 6-2:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO WDTE1 Bit 11/3 CLKOUTEN WDTE0 Bit 10/2 BOREN1 FOSC2 Bit 9/1 BOREN0 FOSC1 Bit 8/0 CPD FOSC0 Register on Page 50
CONFIG1 Legend:
-- = unimplemented locations read as `0'. Shaded cells are not used by reference clock sources.
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NOTES:
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7.0
* * * * * * * *
RESETS
There are multiple ways to reset this device: Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit
To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 7-1.
FIGURE 7-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit RESET Instruction Stack Stack Overflow/Underflow Reset Pointer External Reset MCLR Sleep WDT Time-out Power-on Reset VDD Brown-out Reset BOR Enable Device Reset MCLRE
PWRT Zero LFINTOSC 64 ms
PWRTEN
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7.1 Power-on Reset (POR) 7.2 Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Word 1. The four operating modes are: * * * * BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off
7.1.1
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Word 1. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
Refer to Table 7-3 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Word 2. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 7-3 for more information.
TABLE 7-1:
BOR OPERATING MODES
SBOREN Device Mode BOR Mode Device Device Operation upon Operation upon wake- up from release of POR Sleep Waits for BOR ready(1) Waits for BOR ready Begins immediately Begins immediately Begins immediately
BOREN Config bits BOR_ON (11) BOR_NSLEEP (10) BOR_NSLEEP (10) BOR_SBOREN (01) BOR_SBOREN (01) BOR_OFF (00)
X X X 1 0 X
X Awake Sleep X X X
Active Active Disabled Active Disabled Disabled
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in start-up.
7.2.1
BOR IS ALWAYS ON
7.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word 1 are set to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.
When the BOREN bits of Configuration Word 1 are set to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep.
7.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Word 1 are set to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.
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PIC12F/LF1822/16F/LF1823
FIGURE 7-2:
SBOREN
BROWN-OUT READY
BORRDY
TBORRDY
BOR Protection Active
FIGURE 7-3:
VDD
BROWN-OUT SITUATIONS
VBOR
Internal Reset VDD
TPWRT(1)
VBOR < TPWRT
Internal Reset
TPWRT(1)
VDD
VBOR
Internal Reset Note 1: TPWRT delay only if PWRTE bit is programmed to `0'.
TPWRT(1)
REGISTER 7-1:
R/W-1/u SBOREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
BORCON: BROWN-OUT RESET CONTROL REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-q/u BORRDY bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Word 1 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Word 1 = 01: 1 = BOR Enabled 0 = BOR Disabled Unimplemented: Read as `0' BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive
bit 6-1 bit 0
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Preliminary
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7.3 MCLR 7.8 Power-Up Timer
The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Word 1 and the LVP bit of Configuration Word 2 (Table 7-2). The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. The Power-up Timer is controlled by the PWRTE bit of Configuration Word 1.
TABLE 7-2:
MCLRE 0 1 x
MCLR CONFIGURATION
LVP 0 0 1 MCLR Disabled Enabled Enabled
7.9
Start-up Sequence
Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled).
7.3.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: A Reset does not drive the MCLR pin low.
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 7-4). This is useful for testing purposes or to synchronize more than one device operating in parallel.
7.3.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 12.2 "PORTA Registers" for more information.
7.4
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 10.0 "Watchdog Timer" for more information.
7.5
RESET Instruction
A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to `0'. See Table 7-4 for default conditions after a RESET instruction has occurred.
7.6
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word 2. See Section 3.4.2 "Overflow/Underflow Reset" for more information.
7.7
Programming Mode Exit
Upon exit of Programming mode, the device will behave as if a POR had just occurred.
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PIC12F/LF1822/16F/LF1823
FIGURE 7-4: RESET START-UP SEQUENCE
VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET
Oscillator Modes
External Crystal Oscillator Start-Up Timer Oscillator FOSC TOST
Internal Oscillator Oscillator FOSC
External Clock (EC) CLKIN
FOSC
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Preliminary
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7.10 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 7-3 and Table 7-4 show the Reset conditions of these registers.
TABLE 7-3:
0 0 0 0 u u u u u u 1 u 0 0 0 0 u u u u u u u 1
RESET STATUS BITS AND THEIR SIGNIFICANCE
RMCLR 1 1 1 1 u u u 0 0 u u u RI 1 1 1 1 u u u u u 0 u u POR 0 0 0 u u u u u u u u u BOR x x x 0 u u u u u u u u TO 1 0 x 1 0 0 1 u 1 u u u PD 1 x 0 1 u 0 0 u 0 u u u Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Condition
STKOVF STKUNF
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Condition Program Counter 0000h 0000h 0000h 0000h PC + 1 0000h PC + 1
(1)
STATUS Register ---1 1000 ---u uuuu ---1 0uuu ---0 uuuu ---0 0uuu ---1 1uuu ---1 0uuu ---u uuuu ---u uuuu ---u uuuu
PCON Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up from Sleep Brown-out Reset Interrupt Wake-up from Sleep RESET Instruction Executed Stack Overflow Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1)
0000h 0000h 0000h
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 2: If a Status bit is not implemented, that bit will be read as `0'.
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PIC12F/LF1822/16F/LF1823
7.11 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits to differentiate between a: * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) Stack Overflow Reset (STKOVF) Stack Underflow Reset (STKUNF) MCLR Reset (RMCLR)
The PCON register bits are shown in Register 7-2.
REGISTER 7-2:
R/W/HS-0/q STKOVF bit 7 Legend:
PCON: POWER CONTROL REGISTER
U-0 -- U-0 -- R/W/HC-1/q RMCLR R/W/HC-1/q RI R/W/HC-q/u POR R/W/HC-q/u BOR bit 0 STKUNF
R/W/HS-0/q
HC = Bit is cleared by hardware R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared
HS = Bit is set by hardware U = Unimplemented bit, read as `0' -m/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or set to `0' by firmware STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or set to `0' by firmware Unimplemented: Read as `0' RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)
bit 6
bit 5-4 bit 3
bit 2
bit 1
bit 0
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Preliminary
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TABLE 7-5:
Name BORCON PCON STATUS WDTCON
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Bit 7 Bit 6 -- STKUNF -- -- Bit 5 -- -- -- WDTPS4 Bit 4 -- -- TO WDTPS3 Bit 3 -- RMCLR PD WDTPS2 Bit 2 -- RI Z WDTPS1 Bit 1 -- POR DC Bit 0 BORRDY BOR C Register on Page 77 81 24 101
SBOREN STKOVF -- --
WDTPS0 SWDTEN
Legend: -- = unimplemented bit, reads as `0'. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
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PIC12F/LF1822/16F/LF1823
8.0 INTERRUPTS
The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: * * * * * Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving
Many peripherals produce Interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2.
FIGURE 8-1:
INTERRUPT LOGIC
Wake-up (If in Sleep mode) TMR0IF TMR0IE INTF INTE IOCIF IOCIE From Peripheral Interrupt Logic (Figure 8-2) PEIE Interrupt to CPU
GIE
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PIC12F/LF1822/16F/LF1823
FIGURE 8-2: PERIPHERAL INTERRUPT LOGIC
TMR1GIF TMR1GIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE
CCP1IF CCP1IE TMR1IF TMR1IE TMR2IF TMR2IE EEIF EEIE OSFIF OSFIE C1IF C1IE C2IF(1) C2IE(1) BCLIF BCLIE
To Interrupt Logic (Figure 8-1)
Note 1:
PIC16F/LF1823 only.
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8.1 Operation 8.2 Interrupt Latency
Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: * GIE bit of the INTCON register * Interrupt Enable bit(s) for the specific interrupt event(s) * PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIEx register) The INTCON, PIR1, and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: * Current prefetched instruction is flushed * GIE bit is cleared * Current Program Counter (PC) is pushed onto the stack * Critical registers are automatically saved to the shadow registers (See Section 8.5 "Automatic Context Saving") * PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt's operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles, depending on when the interrupt occurs. See Figure 8-3 and Figure 8-4 for more details.
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Preliminary
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PIC12F/LF1822/16F/LF1823
FIGURE 8-3:
OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTERRUPT LATENCY
CLKOUT
Interrupt Sampled during Q1
Interrupt GIE
PC Execute
PC-1
PC Inst(PC)
PC+1 NOP
0004h NOP
0005h Inst(0004h)
1 Cycle Instruction at PC
Interrupt GIE PC+1/FSR ADDR Inst(PC) New PC/ PC+1 NOP
PC Execute
PC-1
PC
0004h NOP
0005h Inst(0004h)
2 Cycle Instruction at PC
Interrupt GIE
PC Execute
PC-1
PC
FSR ADDR INST(PC)
PC+1 NOP
PC+2 NOP
0004h NOP
0005h Inst(0004h) Inst(0005h)
3 Cycle Instruction at PC
Interrupt GIE
PC Execute
PC-1
PC
FSR ADDR INST(PC)
PC+1 NOP NOP
PC+2 NOP
0004h NOP
0005h Inst(0004h)
3 Cycle Instruction at PC
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PIC12F/LF1822/16F/LF1823
FIGURE 8-4:
Q1 OSC1 CLKOUT (3) INT pin INTF GIE
(1) (5)
INT PIN INTERRUPT TIMING
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(4) (1)
Interrupt Latency (2)
INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 5:
PC
PC + 1 Inst (PC + 1) Inst (PC)
PC + 1 -- Dummy Cycle
0004h Inst (0004h) Dummy Cycle
0005h Inst (0005h) Inst (0004h)
Inst (PC) Inst (PC - 1)
INTF flag is sampled here (every Q1). Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. CLKOUT not available in all oscillator modes. For minimum width of INT pulse, refer to AC specifications in Section 29.0 "Electrical Specifications". INTF is enabled to be set any time during the Q4-Q1 cycles.
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8.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to the Section 9.0 "PowerDown Mode (Sleep)" for more details.
8.4
INT Pin
The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector.
8.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers: * * * * * W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user's application, other registers may also need to be saved.
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8.5.1 INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts.
REGISTER 8-1:
R/W-0/0 GIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0 PEIE R/W-0/0 TMR0IE R/W-0/0 INTE R/W-0/0 IOCIE R/W-0/0 TMR0IF R/W-0/0 INTF R-0/0 IOCIF bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
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PIC12F/LF1822/16F/LF1823
8.5.2 PIE1 REGISTER
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE1 register contains the interrupt enable bits, as shown in Register 8-2.
REGISTER 8-2:
R/W-0/0 TMR1GIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0 ADIE R/W-0/0 RCIE R/W-0/0 TXIE R/W-0/0 SSP1IE R/W-0/0 CCP1IE R/W-0/0 TMR2IE R/W-0/0 TMR1IE bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 Gate Acquisition interrupt 0 = Disables the Timer1 Gate Acquisition interrupt ADIE: A/D Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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8.5.3 PIE2 REGISTER
Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. The PIE2 register contains the interrupt enable bits, as shown in Register 8-3.
REGISTER 8-3:
R/W-0/0 OSFIE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0 C2IE(1) R/W-0/0 C1IE R/W-0/0 EEIE R/W-0/0 BCL1IE U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt C2IE: Comparator C2 Interrupt Enable bit(1) 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt EEIE: EEPROM Write Completion Interrupt Enable bit 1 = Enables the EEPROM Write Completion interrupt 0 = Disables the EEPROM Write Completion interrupt BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt Unimplemented: Read as `0' PIC16F/LF1823 only.
bit 6
bit 5
bit 4
bit 3
bit 2-0 Note 1:
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Preliminary
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PIC12F/LF1822/16F/LF1823
8.5.4 PIR1 REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the interrupt flag bits, as shown in Register 8-4.
REGISTER 8-4:
R/W-0/0 TMR1GIF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0 ADIF R-0/0 RCIF R-0/0 TXIF R/W-0/0 SSP1IF R/W-0/0 CCP1IF R/W-0/0 TMR2IF R/W-0/0 TMR1IF bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending ADIF: A/D Converter Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC12F/LF1822/16F/LF1823
8.5.5 PIR2 REGISTER
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the interrupt flag bits, as shown in Register 8-5.
REGISTER 8-5:
R/W-0/0 OSFIF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0 C2IF(1) R/W-0/0 C1IF R/W-0/0 EEIF R/W-0/0 BCL1IF U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending C2IF: Comparator C2 Interrupt Flag bit(1) 1 = Interrupt is pending 0 = Interrupt is not pending C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending EEIF: EEPROM Write Completion Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Unimplemented: Read as `0' PIC16F/LF1823 only.
bit 6
bit 5
bit 4
bit 3
bit 2-0 Note 1:
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TABLE 8-1:
Name INTCON OPTION_REG PIE1 PIE2 PIR1 PIR2 Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7 GIE WPUEN TMR1GIE OSFIE TMR1GIF OSFIF Bit 6 PEIE INTEDG ADIE C2IE(1) ADIF C2IF(1) Bit 5 TMR0IE TMR0CS RCIE C1IE RCIF C1IF Bit 4 INTE TMR0SE TXIE EEIE TXIF EEIF Bit 3 IOCIE PSA SSP1IE BCL1IE SSP1IF BCL1IF Bit 2 TMR0IF PS2 CCP1IE -- CCP1IF -- Bit 1 INTF PS1 TMR2IE -- TMR2IF -- Bit 0 IOCIF PS0 TMR1IE -- TMR1IF -- Register on Page 89 171 90 91 92 93
-- = unimplemented locations read as `0'. Shaded cells are not used by Interrupts. PIC16F/LF1823 only.
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9.0 POWER-DOWN MODE (SLEEP)
9.1 Wake-up from Sleep
The Power-Down mode is entered by executing a SLEEP instruction. Upon entering Sleep mode, the following conditions exist: WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. 6. Timer1 oscillator is unaffected and peripherals that operate from it may continue operation in Sleep. 7. ADC is unaffected, if the dedicated FRC clock is selected. 8. Capacitive Sensing oscillator is unaffected. 9. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance). 10. Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: * * * * * * I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using Timer1 oscillator 1. The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. 6. External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)
The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 7.10 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.
I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these modules.
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9.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
FIGURE 9-1:
OSC1(1) CLKOUT(2) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(3) Interrupt Latency (4) Processor in Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
PC Inst(PC) = Sleep Inst(PC - 1)
PC + 1 Inst(PC + 1) Sleep
PC + 2
PC + 2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
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TABLE 9-1:
Name INTCON IOCAF IOCAN IOCAP PIE1 PIE2 PIR1 PIR2 STATUS WDTCON Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Bit 7 GIE -- -- -- Bit 6 PEIE -- -- -- ADIE C2IE C2IF -- --
(1)
Bit 5 TMR0IE IOCAF5 IOCAN5 IOCAP5 RCIE C1IE RCIF C1IF -- WDTPS4
Bit 4 INTE IOCAF4 IOCAN4 IOCAP4 TXIE EEIE TXIF EEIF TO WDTPS3
Bit 3 IOCIE IOCAF3 IOCAN3 IOCAP3 SSP1IE BCL1IE SSP1IF BCL1IF PD WDTPS2
Bit 2 TMR0IF IOCAF2 IOCAN2 IOCAP2 CCP1IE -- CCP1IF -- Z WDTPS1
Bit 1 INTF IOCAF1 IOCAN1 IOCAP1 TMR2IE -- TMR2IF -- DC WDTPS0
Bit 0 IOCIF IOCAF0 IOCAN0 IOCAP0 TMR1IE -- TMR1IF -- C SWDTEN
Register on Page 89 128 128 128 90 91 92 93 24 101
TMR1GIE OSFIE TMR1GIF OSFIF -- --
ADIF
(1)
-- = unimplemented, read as `0'. Shaded cells are not used in Power-down mode. PIC16F/LF1823 only.
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10.0 WATCHDOG TIMER
The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: * Independent clock source * Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off * Configurable time-out period is from 1 ms to 268 seconds (typical) * Multiple Reset conditions * Operation during Sleep
FIGURE 10-1:
WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep
WATCHDOG TIMER BLOCK DIAGRAM
LFINTOSC
23-bit Programmable Prescaler WDT
WDT Time-out
WDTPS<4:0>
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10.1 Independent Clock Source 10.3 Time-Out Period
The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. The WDTPS bits of the WDTCON register set the time-out period from 1ms to 268 seconds. After a Reset, the default time-out period is 2 seconds.
10.2
WDT Operating Modes
The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 10-1.
10.4
Clearing the WDT
The WDT is cleared when any of the following conditions occur: * * * * * * * Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail event WDT is disabled OST is running
10.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to `11', the WDT is always on. WDT protection is active during Sleep.
10.2.2
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to `10', the WDT is on, except in Sleep. WDT protection is not active during Sleep.
See Table 10-2 for more information.
10.5
Operation During Sleep
10.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word 1 are set to `01', the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged Table 10-1 for more details. by Sleep. See
When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See Section 3.0 "Memory Organization" and The STATUS register (Register 3-1) for more information.
TABLE 10-1:
WDTE Config bits WDT_ON (11)
WDT OPERATING MODES
SWDTEN X X X 1 0 X Device Mode X Awake Sleep X X X WDT Mode Active Active Disabled Active Disabled Disabled
WDT_NSLEEP (10) WDT_NSLEEP (10) WDT_SWDTEN (01) WDT_SWDTEN (01) WDT_OFF (00)
TABLE 10-2:
WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) Cleared until the end of OST Unaffected Cleared
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REGISTER 10-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WDTPS<4:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 00000 = 1:32 (Interval 1 ms typ) 00001 = 1:64 (Interval 2 ms typ) 00010 = 1:128 (Interval 4 ms typ) 00011 = 1:256 (Interval 8 ms typ) 00100 = 1:512 (Interval 16 ms typ) 00101 = 1:1024 (Interval 32 ms typ) 00110 = 1:2048 (Interval 64 ms typ) 00111 = 1:4096 (Interval 128 ms typ) 01000 = 1:8192 (Interval 256 ms typ) 01001 = 1:16384 (Interval 512 ms typ) 01010 = 1:32768 (Interval 1s typ) 01011 = 1:65536 (Interval 2s typ) (Reset value) 01100 = 1:131072 (217) (Interval 4s typ) 01101 = 1:262144 (218) (Interval 8s typ) 01110 = 1:524288 (219) (Interval 16s typ) 01111 = 1:1048576 (220) (Interval 32s typ) 10000 = 1:2097152 (221) (Interval 64s typ) 10001 = 1:4194304 (222) (Interval 128s typ) 10010 = 1:8388608 (223) (Interval 256s typ) 10011 = Reserved. Results in minimum interval (1:32) * * * 11111 = Reserved. Results in minimum interval (1:32) bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. U = Unimplemented bit, read as `0' -m/n = Value at POR and BOR/Value at all other Resets
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- R/W-0/0 WDTPS4 R/W-1/1 WDTPS3 R/W-0/0 WDTPS2 R/W-1/1 WDTPS1 R/W-1/1 WDTPS0 R/W-0/0 SWDTEN bit 0
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11.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL
11.1 EEADRL and EEADRH Registers
The EEADRH:EEADRL register pair can address up to a maximum of 256 bytes of data EEPROM or up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the EEADRH register and the LSB is written to the EEADRL register. When selecting a EEPROM address value, only the LSB of the address is written to the EEADRL register.
The Data EEPROM and Flash program memory are readable and writable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs). There are six SFRs used to access these memories: * * * * * * EECON1 EECON2 EEDATL EEDATH EEADRL EEADRH
11.1.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, any subsequent operations will operate on the EEPROM memory. When set, any subsequent operations will operate on the program memory. On Reset, EEPROM is selected by default. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. Interrupt flag bit EEIF of the PIR2 register is set when write is complete. It must be cleared in the software. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the data EEPROM write sequence. To enable writes, a specific pattern must be written to EECON2.
When interfacing the data memory block, EEDATL holds the 8-bit data for read/write, and EEADRL holds the address of the EEDATL location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh. When accessing the program memory block, the EEDATH:EEDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the EEADRL and EEADRH registers form a 2-byte word that holds the 15-bit address of the program memory location being read. The EEPROM data memory allows byte read and write. An EEPROM byte write automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. Depending on the setting of the Flash Program Memory Self Write Enable bits WRT<1:0> of the Configuration Word 2, the device may or may not be able to write certain blocks of the program memory. However, reads from the program memory are always allowed. When the device is code-protected, the device programmer can no longer access data or program memory. When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory.
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11.2 Using the Data EEPROM
11.2.2
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). When variables in one section change frequently, while variables in another section do not change, it is possible to exceed the total number of write cycles to the EEPROM without exceeding the total number of write cycles to a single byte. Refer to Section 29.0 "Electrical Specifications". If this is the case, then a refresh of the array must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory.
WRITING TO THE DATA EEPROM MEMORY
To write an EEPROM data location, the user must first write the address to the EEADRL register and the data to the EEDATL register. Then the user must follow a specific sequence to initiate the write for each byte. The write will not initiate if the above sequence is not followed exactly (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
11.2.1
READING THE DATA EEPROM MEMORY
To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD and CFGS control bits of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
EXAMPLE 11-1:
DATA EEPROM READ
11.2.3
BANKSEL EEADRL ; MOVLW DATA_EE_ADDR ; MOVWF EEADRL ;Data Memory ;Address to read BCF EECON1, CFGS ;Deselect Config space BCF EECON1, EEPGD;Point to DATA memory BSF EECON1, RD ;EE Read MOVF EEDATL, W ;W = EEDATL
PROTECTION AGAINST SPURIOUS WRITE
There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during: * Brown-out * Power Glitch * Software Malfunction
Note:
Data EEPROM can be read regardless of the setting of the CPD bit.
11.2.4
DATA EEPROM OPERATION DURING CODE-PROTECT
Data memory can be code-protected by programming the CPD bit in the Configuration Word 1 (Register 5-1) to `0'. When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM. It is recommended to code-protect the program memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM.
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EXAMPLE 11-2:
BANKSEL MOVLW MOVWF MOVLW MOVWF BCF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BTFSC GOTO
DATA EEPROM WRITE
EEADRL DATA_EE_ADDR EEADRL DATA_EE_DATA EEDATL EECON1, CFGS EECON1, EEPGD EECON1, WREN INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EECON1, $-2 GIE ; ; ;Data Memory Address to write ; ;Data Memory Value to write ;Deselect Configuration space ;Point to DATA memory ;Enable writes ;Disable INTs. ; ;Write 55h ; ;Write AAh ;Set WR bit to begin write ;Enable Interrupts ;Disable writes ;Wait for write to complete ;Done
Required Sequence
WR GIE WREN WR
FIGURE 11-1:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
PC
PC + 1
EEADRH,EEADRL
PC + 3 PC+3
PC + 4
PC + 5
Flash Data
INSTR (PC)
INSTR (PC + 1)
EEDATH,EEDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC - 1) executed here
BSF EECON1,RD executed here
INSTR(PC + 1) executed here
Forced NOP executed here
INSTR(PC + 3) executed here
INSTR(PC + 4) executed here
RD bit
EEDATH EEDATL Register
EERHLT
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11.3 Flash Program Memory Overview
11.3.1
It is important to understand the Flash program memory structure for erase and programming operations. Flash Program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum block size that can be erased by user software. Flash program memory may only be written or erased if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT<1:0> of Configuration Word 2. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the EEDATH:EEDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase.
READING THE FLASH PROGRAM MEMORY
To read a program memory location, the user must: 1. 2. 3. 4. Write the Least and Most Significant address bits to the EEADRH:EEADRL register pair. Clear the CFGS bit of the EECON1 register. Set the EEPGD control bit of the EECON1 register. Then, set control bit RD of the EECON1 register.
Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle, in the EEDATH:EEDATL register pair; therefore, it can be read as two bytes in the following instructions. EEDATH:EEDATL register pair will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit.
The number of data write latches is not equivalent to the number of row locations. During programming, user software will need to fill the set of write latches and initiate a programming operation multiple times in order to fully reprogram an erased row. For example, a device with a row size of 32 words and eight write latches will need to load the write latches with data and initiate a programming operation four times. The size of a program memory row and the number of program memory write latches may vary by device. See Table 11-1 for details.
TABLE 11-1:
FLASH MEMORY ORGANIZATION BY DEVICE
Erase Block (Row) Size/ Boundary 16 words, EEADRL<3:0> = 0000 Number of Write Latches/ Boundary 16 words, EEADRL<3:0> = 0000
Device PIC12F/LF1822/ 16F/LF1823
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EXAMPLE 11-3: FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWL BCF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL PROG_ADDR_HI EEADRH EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,RD ; Select Bank for EEPROM registers ; ; Store LSB of address ; ; Store MSB of address ; ; ; ; ; ; ; ; ; ; ; Do not select Configuration Space Select Program Memory Disable interrupts Initiate read Executed (Figure 11-1) Ignored (Figure 11-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location
INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI
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11.3.2 ERASING FLASH PROGRAM MEMORY
While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. 6. Load the EEADRH:EEADRL register pair with the address of new row to be erased. Clear the CFGS bit of the EECON1 register. Set the EEPGD, FREE, and WREN bits of the EECON1 register. Write 55h, then AAh, to EECON2 (Flash programming unlock sequence). Set control bit WR of the EECON1 register to begin the erase operation. Poll the FREE bit in the EECON1 register to determine when the row erase has completed. The following steps should be completed to load the write latches and program a block of program memory. These steps are divided into two parts. First, all write latches are loaded with data except for the last program memory location. Then, the last write latch is loaded and the programming sequence is initiated. A special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. This unlock sequence should not be interrupted. Set the EEPGD and WREN bits of the EECON1 register. 2. Clear the CFGS bit of the EECON1 register. 3. Set the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is `1', the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the EEADRH:EEADRL register pair with the address of the location to be written. 5. Load the EEDATH:EEDATL register pair with the program memory data to be written. 6. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The write latch is now loaded. 7. Increment the EEADRH:EEADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the EECON1 register. When the LWLO bit of the EECON1 register is `0', the write sequence will initiate the write to Flash program memory. 10. Load the EEDATH:EEDATL register pair with the program memory data to be written. 11. Write 55h, then AAh, to EECON2, then set the WR bit of the EECON1 register (Flash programming unlock sequence). The entire latch block is now written to Flash program memory. It is not necessary to load the entire write latch block with user program data. However, the entire write latch block will be written to program memory. An example of the complete write sequence for eight words is shown in Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Note: The code sequence provided in Example 11-5 must be repeated multiple times to fully program an erased program memory row. 1.
See Example 11-4. After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
11.3.3
WRITING TO FLASH PROGRAM MEMORY
Program memory is programmed using the following steps: 1. 2. 3. 4. Load the starting address of the word(s) to be programmed. Load the write latches with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 11-2 (block writes to program memory with 16 write latches) for more details. The write latches are aligned to the address boundary defined by EEADRL as shown in Table 11-1. Write operations do not cross these boundaries. At the completion of a program memory write operation, the write latches are reset to contain 0x3FFF.
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After the "BSF EECON1,WR" instruction, the processor requires two cycles to set up the write operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the write takes place (i.e., the last word of the block write). This is not Sleep mode as the clocks and peripherals will continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
7 5 EEDATH 07 EEDATA 0
6
First word of block to be written
8
Last word of block to be written
14
EEADRL<3:0> = 0000 EEADRL<3:0> = 0001
14
EEADRL<3:0> = 0010
14
EEADRL<3:0> = 1111
14
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
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EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following: ; 1. A valid address within the erase block is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF BANKSEL MOVF MOVWF MOVF MOVWF BSF BCF BSF BSF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP
INTCON,GIE EEADRL ADDRL,W EEADRL ADDRH,W EEADRH EECON1,EEPGD EECON1,CFGS EECON1,FREE EECON1,WREN 55h EECON2 0AAh EECON2 EECON1,WR
; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; ; ; ; ; ; ; ; ; ; ; ; Point to program memory Not configuration space Specify an erase operation Enable writes Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase Any instructions here are ignored as processor halts to begin erase sequence Processor will stop here and wait for erase complete.
Required Sequence
; after erase processor continues with 3rd instruction BCF BSF EECON1,WREN INTCON,GIE ; Disable writes ; Enable interrupts
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EXAMPLE 11-5:
; ; ; ; ; ; ;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following: 1. The 16 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF INTCON,GIE EEADRH ADDRH,W EEADRH ADDRL,W EEADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,LWLO FSR0++ EEDATL FSR0++ EEDATH EEADRL,W 0x07 0x07 STATUS,Z START_WRITE 55h EECON2 0AAh EECON2 EECON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address
Load initial data address Load initial data address Point to program memory Not configuration space Enable writes Only Load Write Latches
LOOP MOVIW MOVWF MOVIW MOVWF MOVF XORLW ANDLW BTFSC GOTO MOVLW MOVWF MOVLW MOVWF BSF NOP NOP ; Load first data byte into lower ; ; Load second data byte into upper ; ; Check if lower bits of address are '000' ; Check if we're on the last of 8 addresses ; ; Exit if last of eight words, ; ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write to complete.
Required Sequence
; After write processor continues with 3rd instruction. INCF GOTO START_WRITE BCF EEADRL,F LOOP ; Still loading latches Increment address ; Write next latches
EECON1,LWLO
; No more loading latches - Actually start Flash program ; memory write ; ; ; ; ; ; ; ; Start of required write sequence: Write 55h Write AAh Set WR bit to begin write Any instructions here are ignored as processor halts to begin write sequence Processor will stop here and wait for write complete.
MOVLW MOVWF MOVLW MOVWF BSF NOP NOP
Required Sequence
55h EECON2 0AAh EECON2 EECON1,WR
BCF BSF
EECON1,WREN INTCON,GIE
; after write processor continues with 3rd instruction ; Disable writes ; Enable interrupts
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Preliminary
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11.4 Modifying Flash Program Memory 11.5
When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. 8. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. Repeat steps 6 and 7 as many times as required to reprogram the erased row.
User ID, Device ID and Configuration Word Access
Instead of accessing program memory or EEPROM data memory, the User ID's, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the EECON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EEDATL register pair is cleared.
TABLE 11-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Function User IDs Device ID/Revision ID Configuration Words 1 and 2 Read Access Yes Yes Yes Write Access Yes No No
Address 8000h-8003h 8006h 8007h-8008h
EXAMPLE 11-3:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF BSF BCF BSF NOP NOP BSF MOVF MOVWF MOVF MOVWF EEADRL PROG_ADDR_LO EEADRL EEADRH EECON1,CFGS INTCON,GIE EECON1,RD ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address ; ; ; ; ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 11-1) Ignored (See Figure 11-1) Restore interrupts Get LSB of word Store in user location Get MSB of word Store in user location
INTCON,GIE EEDATL,W PROG_DATA_LO EEDATH,W PROG_DATA_HI
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11.6 Write Verify
Depending on the application, good programming practice may dictate that the value written to the data EEPROM or program memory should be verified (see Example 11-6) to the desired value to be written. Example 11-6 shows how to verify a write to EEPROM.
EXAMPLE 11-6:
BANKSEL EEDATL MOVF EEDATL, W BSF XORWF BTFSS GOTO :
EEPROM WRITE VERIFY
; ;EEDATL not changed ;from previous write EECON1, RD ;YES, Read the ;value written EEDATL, W ; STATUS, Z ;Is data the same WRITE_ERR ;No, handle error ;Yes, continue
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Preliminary
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PIC12F/LF1822/16F/LF1823
REGISTER 11-1:
R/W-x/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared EEDAT<7:0>: Read/write value for EEPROM data byte or Least Significant bits of program memory U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEDATL: EEPROM DATA REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 EEDAT<7:0>
REGISTER 11-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
EEDATH: EEPROM DATA HIGH BYTE REGISTER
U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 EEDAT<13:8>
W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0'
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-3:
R/W-0/0 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
EEADRL: EEPROM ADDRESS REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 EEADR<7:0>
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEADR<7:0>: Specifies the Least Significant bits for program memory address or EEPROM address
REGISTER 11-4:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-0
EEADRH: EEPROM ADDRESS HIGH BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> bit 0 R/W-0/0 R/W-0/0 R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0'
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EEADR<14:8>: Specifies the Most Significant bits for program memory address or EEPROM address
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REGISTER 11-5:
R/W-0/0 EEPGD bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware
EECON1: EEPROM CONTROL 1 REGISTER
R/W-0/0 LWLO R/W/HC-0/0 FREE R/W-x/q WRERR R/W-0/0 WREN R/S/HC-0/0 WR R/S/HC-0/0 RD bit 0 CFGS
R/W-0/0
EEPGD: Flash Program/Data EEPROM Memory Select bit 1 = Accesses program space Flash memory 0 = Accesses data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Accesses Configuration, User ID and Device ID Registers 0 = Accesses Flash Program or data EEPROM Memory LWLO: Load Write Latches Only bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = The next WR command does not initiate a write; only the program memory latches are updated. 0 = The next WR command writes a value from EEDATH:EEDATL into program memory latches and initiates a write of all the data stored in the program memory latches. If CFGS = 0 and EEPGD = 0: (Accessing data EEPROM) LWLO is ignored. The next WR command initiates a write to the data EEPROM.
bit 6
bit 5
bit 4
FREE: Program Flash Erase Enable bit If CFGS = 1 (Configuration space) OR CFGS = 0 and EEPGD = 1 (program Flash): 1 = Performs an erase operation on the next WR command (cleared by hardware after completion of erase). 0 = Performs a write operation on the next WR command. If EEPGD = 0 and CFGS = 0: (Accessing data EEPROM) FREE is ignored. The next WR command will initiate both a erase cycle and a write cycle.
bit 3
WRERR: EEPROM Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write `1') of the WR bit). 0 = The program or erase operation completed normally. WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash and data EEPROM WR: Write Control bit 1 = Initiates a program Flash or data EEPROM program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash or data EEPROM is complete and inactive. RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash or data EEPROM data read.
bit 2
bit 1
bit 0
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REGISTER 11-6:
W-0/0 bit 7 Legend: R = Readable bit S = Bit can only be set `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Data EEPROM Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the EECON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. Refer to Section 11.2.2 "Writing to the Data EEPROM Memory" for more information. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
EECON2: EEPROM CONTROL 2 REGISTER
W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 bit 0 EEPROM Control Register 2
TABLE 11-3:
Name EECON1 EECON2 EEADRL EEADRH EEDATL EEDATH INTCON PIE2 PIR2
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Bit 6 CFGS Bit 5 LWLO Bit 4 FREE Bit 3 WRERR Bit 2 WREN Bit 1 WR Bit 0 RD Register on Page 115 116* 114 114 114 114 INTF -- -- IOCIF -- -- 89 91 93 TMR0IF -- --
Bit 7 EEPGD
EEPROM Control Register 2 (not a physical register) EEADRL<7:0> -- -- GIE OSFIE OSFIF -- PEIE C2IE(1) C2IF(1) TMR0IE C1IE C1IF INTE EEIE EEIF EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> IOCIE BCL1IE BCL1IF
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Data EEPROM module. * Page provides register information. Note 1: PIC16F/LF1823 only.
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12.0 I/O PORTS
12.1 Alternate Pin Function
Depending on the device selected and peripherals enabled, there are up to two ports available. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRISx registers (data direction register) * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same affect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports with analog functions also have an ANSELx register which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 12-1. The Alternate Pin Function Control (APFCON) registers are used to steer specific peripheral input and output functions between different pins. The APFCON registers are shown in Register 12-1. For this device family, the following functions can be moved between different pins. * * * * * * RX/DT/TX/CK SDO SS (Slave Select) T1G P1B CCP1/P1A
These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected.
FIGURE 12-1:
GENERIC I/O PORT OPERATION
Read LATx D Write LATx Write PORTx Q
TRISx
CK Data Register
VDD
Data Bus I/O pin Read PORTx To peripherals ANSELx
VSS
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REGISTER 12-1:
R/W-0/0 RXDTSEL bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared RXDTSEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = RX/DT function is on RA1 1 = RX/DT function is on RA5 For 14 Pin Devices (PIC16F/LF1823): 0 = RX/DT function is on RC5 1 = RX/DT function is on RA1 SDOSEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = SDO function is on RA0 1 = SDO function is on RA4 For 14 Pin Devices (PIC16F/LF1823): 0 = SDO function is on RC2 1 = SDO function is on RA4 SSSEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = SS function is on RA3 1 = SS function is on RA0 For 14 Pin Devices (PIC16F/LF1823): 0 = SS function is on RC3 1 = SS function is on RA3 Unimplemented: Read as `0' T1GSEL: Pin Selection bit 0 = T1G function is on RA4 1 = T1G function is on RA3 TXCKSEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = TX/CK function is on RA0 1 = TX/CK function is on RA4 For 14 Pin Devices (PIC16F/LF1823): 0 = TX/CK function is on RC4 1 = TX/CK function is on RA0 P1BSEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = P1B function is on RA0 1 = P1B function is on RA4 For 14 Pin Devices (PIC16F/LF1823): P1B function is always on RC4 CCP1SEL: Pin Selection bit For 8 Pin Devices (PIC12F/LF1822): 0 = CCP1/P1A function is on RA2 1 = CCP1/P1A function is on RA5 For 14 Pin Devices (PIC16F/LF1823): CCP1/P1A function is always on RC5 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0 SSSEL U-0 -- R/W-0/0 T1GSEL R/W-0/0 TXCKSEL R/W-0/0 P1BSEL R/W-0/0 CCP1SEL bit 0
R/W-0/0 SDOSEL
bit 6
bit 5
bit 4 bit 3
bit 2
bit 1
bit 0
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12.2 PORTA Registers
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 12-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as `1'. Example 12-1 shows how to initialize PORTA. Reading the PORTA register (Register 12-2) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). The TRISA register (Register 12-3) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'.
12.2.1
ANSELA REGISTER
The ANSELA register (Register 12-5) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 12-1:
BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTA
; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs
PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA
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12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES
RA3 No output priorities. Input only pin. RA4 1. 2. 3. 4. 5. 6. 7. RA5 1. 2. 3. 4. 5. OSC1 T1OSI (Timer1 Oscillator) SRNQ (PIC12F/LF1822 only) RX/DT (PIC12F/LF1822 only) CCP1/P1A (PIC12F/LF1822 only) OSC2 CLKOUT T1OSO CLKR TX/CK (PIC12F/LF1822 only) SDO P1B (PIC12F/LF1822 only) Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input functions, such as ADC, comparator and CapSense inputs, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog mode with the priority shown below. RA0 1. 2. 3. 4. 5. 6. 7. RA1 1. 2. 3. 4. 5. RA2 1. 2. 3. 4. SRQ C1OUT (Comparator) SDA (PIC12F/LF1822 only) CCP1/P1A (PIC12F/LF1822 only) ICSPCLK ICDCLK SCL (PIC12F/LF1822 only) RX/DT (EUSART) SCK (PIC12F/LF1822 only) ICSPDAT ICDDAT DACOUT (DAC) MDOUT (PIC12F/LF1822 only) TX/CK (EUSART) SDO (PIC12F/LF1822 only) P1B (PIC12F/LF1822 only)
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REGISTER 12-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PORTA: PORTA REGISTER
U-0 -- R/W-x/x RA5 R/W-x/x RA4 R-x/x RA3 R/W-x/x RA2 R/W-x/x RA1 R/W-x/x RA0 bit 0
Note 1:
REGISTER 12-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-4
TRISA: PORTA TRI-STATE REGISTER
U-0 -- R/W-1/1 TRISA5 R/W-1/1 TRISA4 R-1/1 TRISA3 R/W-1/1 TRISA2 R/W-1/1 TRISA1 R/W-1/1 TRISA0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0 TRISA<5:4>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output TRISA3: RA3 Port Tri-State Control bit This bit is always `1' as RA3 is an input only TRISA<2:0>: PORTA Tri-State Control bits 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output
bit 3 bit 2-0
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REGISTER 12-4:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-4 bit 3 bit 2-0 Note 1: W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0 LATA<5:4>: RA<5:4> Output Latch Value bits(1) Unimplemented: Read as `0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
LATA: PORTA DATA LATCH REGISTER
U-0 -- R/W-x/u LATA5 R/W-x/u LATA4 U-0 -- R/W-x/u LATA2 R/W-x/u LATA1 R/W-x/u LATA0 bit 0
REGISTER 12-5:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4
ANSELA: PORTA ANALOG SELECT REGISTER
U-0 -- U-0 -- R/W-1/1 ANSA4 U-0 -- R/W-1/1 ANSA2 R/W-1/1 ANSA1 R/W-1/1 ANSA0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. Unimplemented: Read as `0' ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.
bit 3 bit 2-0
Note 1:
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REGISTER 12-6:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WPUB<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
WPUA: WEAK PULL-UP PORTA REGISTER
U-0 -- R/W-1/1 WPUA5 R/W-1/1 WPUA4 R/W-1/1 WPUA3 R/W-1/1 WPUA2 R/W-1/1 WPUA1 R/W-1/1 WPUA0 bit 0
Note 1: 2:
TABLE 12-1:
Name ANSELA APFCON LATA OPTION_REG PORTA TRISA WPUA Legend: Note 1: 2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- RXDTSEL -- WPUEN -- -- -- Bit 6 -- SDOSEL -- INTEDG -- -- -- Bit 5 -- SSSEL LATA5 TMR0CS RA5 TRISA5 WPUA5 Bit 4 ANSA4 --LATA4 TMR0SE RA4 TRISA4 WPUA4 Bit 3 -- T1GSEL -- PSA RA3 TRISA3 WPUA3 RA2 TRISA2 WPUA2 Bit 2 ANSA2 TXCKSEL LATA2 Bit 1 ANSA1 P1BSEL LATA1 PS<2:0> RA1 TRISA1 WPUA1 RA0 TRISA0 WPUA0 Bit 0 ANSA0 CCP1SEL LATA0 Register on Page 122 118 122 171 121 121 123
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. PIC12F1822/16F1823 only. PIC16F/LF1823 only.
TABLE 12-2:
Name Bits 13:8 7:0
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit -/7 -- CP Bit -/6 -- MCLRE Bit 13/5 FCMEN PWRTE Bit 12/4 IESO Bit 11/3 CLKOUTEN Bit 10/2 Bit 9/1 Bit 8/0 CPD Register on Page 50
CONFIG1 Legend: Note 1:
BOREN<1:0> FOSC<2:0>
WDTE<1:0>
-- = unimplemented location, read as `0'. Shaded cells are not used by PORTA. PIC12F1822/16F1823 only.
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Preliminary
DS41413A-page 123
PIC12F/LF1822/16F/LF1823
12.3 PORTC Registers (PIC16F/LF1823 only)
12.3.2 PORTC FUNCTIONS AND OUTPUT PRIORITIES
Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the lowest number in the following lists. Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output. Certain digital input functions override other port functions and are included in the priority list. RC0 1. 2. RC1 1. RC2 1. 2. 1. RC4 1. 2. 3. 4. 5. RC5 1. 2. RX/DT CCP1/P1A MDOUT SRNQ C2OUT TX/CK P1B SDO (MSSP) P1D P1C SDA (MSSP) SCL (MSSP) SCK (MSSP)
PORTC is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 12-8). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 12-2 shows how to initialize PORTC. Reading the PORTC register (Register 12-7) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). The TRISC register (Register 12-8) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read `0'.
12.3.1
ANSELC REGISTER
RC3
The ANSELC register (Register 12-10) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no affect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELC register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read `0'.
EXAMPLE 12-2:
BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF
INITIALIZING PORTC
PORTC ; PORTC ;Init PORTC LATC ;Data Latch LATC ; ANSELC ANSELC ;Make RC<5:0> digital TRISB ; B'00110000';Set RC<5:4> as inputs ;and RC<3:0> as outputs TRISC ;
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REGISTER 12-7:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' RC<5:0>: PORTC General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PORTC: PORTC REGISTER
U-0 -- R/W-x/u RC5 R/W-x/u RC4 R/W-x/u RC3 R/W-x/u RC2 R/W-x/u RC1 R/W-x/u RC0 bit 0
REGISTER 12-8:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
TRISC: PORTC TRI-STATE REGISTER
U-0 -- R/W-1/1 TRISC5 R/W-1/1 TRISC4 R/W-1/1 TRISC3 R/W-1/1 TRISC2 R/W-1/1 TRISC1 R/W-1/1 TRISC0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' TRISC<5:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output
REGISTER 12-9:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 Note 1:
LATC: PORTC DATA LATCH REGISTER
U-0 -- R/W-x/u LATC5 R/W-x/u LATC4 R/W-x/u LATC3 R/W-x/u LATC2 R/W-x/u LATC1 R/W-x/u LATC0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' LATC<5:0>: PORTC Output Latch Value bits(1) Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.
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Preliminary
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PIC12F/LF1822/16F/LF1823
REGISTER 12-10: ANSELC: PORTC ANALOG SELECT REGISTER
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets U-0 -- U-0 -- U-0 -- R/W-1/1 ANSC3 R/W-1/1 ANSC2 R/W-1/1 ANSC1 R/W-1/1 ANSC0 bit 0
Note 1:
REGISTER 12-11: WPUC: WEAK PULL-UP PORTC REGISTER
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' WPUC<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is in configured as an output. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets U-0 -- R/W-1/1 WPUC5 R/W-1/1 WPUC4 R/W-1/1 WPUC3 R/W-1/1 WPUC2 R/W-1/1 WPUC1 R/W-1/1 WPUC0 bit 0
Note 1: 2:
TABLE 12-3:
Name ANSELC LATC OPTION_REG PORTC TRISC WPUC Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC(1)
Bit 7 -- -- WPUEN -- -- -- Bit 6 -- -- INTEDG -- -- -- Bit 5 -- LATC5 TMR0CS RC5 TRISC5 WPUC5 Bit 4 -- LATC4 TMR0SE RC4 TRISC4 WPUC4 Bit 3 ANSC3 LATC3 PSA RC3 TRISC3 WPUC3 RC2 TRISC2 WPUC2 Bit 2 ANSC2 LATC2 Bit 1 ANSC1 LATC1 PS<2:0> RC1 TRISC1 WPUC1 RC0 TRISC0 WPUC0 Bit 0 ANSC0 LATC0 Register on Page 126 125 171 125 125 126
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTC. PIC16F/LF1823 only.
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PIC12F/LF1822/16F/LF1823
13.0 INTERRUPT-ON-CHANGE
13.3 Interrupt Flags
The PORTA pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTA pin, or combination of PORTA pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags The IOCAFx bits located in the IOCAF register are status flags that correspond to the Interrupt-on-change pins of PORTA. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCAFx bits.
13.4
Clearing Interrupt Flags
Figure 13-1 is a block diagram of the IOC module.
13.1
Enabling the Module
The individual status flags, (IOCAFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed.
To allow individual PORTA pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.
13.2
Individual Pin Configuration
EXAMPLE 13-1:
MOVLW XORWF ANDWF 0xff IOCAF, W IOCAF, F
For each PORTA pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCAPx bit of the IOCAP register is set. To enable a pin to detect a falling edge, the associated IOCANx bit of the IOCAN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCAPx bit and the IOCANx bit of the IOCAP and IOCAN registers, respectively.
13.5
Operation in Sleep
The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCAF register will be updated prior to the first instruction executed out of Sleep.
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCIE
IOCANx
D CK R
Q
IOCAFx From all other IOCAFx individual pin detectors IOC Interrupt to CPU Core
RAx
IOCAPx
D CK R
Q
Q2 Clock Cycle
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Preliminary
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PIC12F/LF1822/16F/LF1823
REGISTER 13-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0 -- R/W-0/0 IOCAP5 R/W-0/0 IOCAP4 R/W-0/0 IOCAP3 R/W-0/0 IOCAP2 R/W-0/0 IOCAP1 R/W-0/0 IOCAP0 bit 0
REGISTER 13-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0 -- R/W-0/0 IOCAN5 R/W-0/0 IOCAN4 R/W-0/0 IOCAN3 R/W-0/0 IOCAN2 R/W-0/0 IOCAN1 R/W-0/0 IOCAN0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0 -- R/W/HS-0/0 IOCAF5 R/W/HS-0/0 IOCAF4 R/W/HS-0/0 IOCAF3 R/W/HS-0/0 IOCAF2 R/W/HS-0/0 IOCAF1 R/W/HS-0/0 IOCAF0 bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware
Unimplemented: Read as `0' IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change.
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TABLE 13-1:
Name ANSELA INTCON IOCAF IOCAN IOCAP TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7 -- GIE -- -- -- -- Bit 6 -- PEIE -- -- -- -- Bit 5 -- TMR0IE IOCAF5 IOCAN5 IOCAP5 TRISA5 Bit 4 ANSA4 INTE IOCAF4 IOCAN4 IOCAP4 TRISA4 Bit 3 -- IOCIE IOCAF3 IOCAN3 IOCAP3 TRISA3 Bit 2 ANSA2 TMR0IF IOCAF2 IOCAN2 IOCAP2 TRISA2 Bit 1 ANSA1 INTF IOCAF1 IOCAN1 IOCAP1 TRISA1 Bit 0 ANSA0 IOCIF IOCAF0 IOCAN0 IOCAP0 TRISA0 Register on Page 122 89 128 128 128 121
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Interrupt-on-Change.
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Preliminary
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PIC12F/LF1822/16F/LF1823
NOTES:
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PIC12F/LF1822/16F/LF1823
14.0 FIXED VOLTAGE REFERENCE (FVR)
14.1 Independent Gain Amplifiers
The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 15.0 "Analog-to-Digital Converter (ADC) Module" for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Reference Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 18.0 "Comparator Module" for additional information.
The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * * * * ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC)
The FVR can be enabled by setting the FVREN bit of the FVRCON register.
14.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Section 29.0 "Electrical Specifications" for the minimum delay requirement.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0> 2
X1 X2 X4
FVR BUFFER1 (To ADC Module)
CDAFVR<1:0>
2
X1 X2 X4
FVR BUFFER2 (To Comparators, DAC)
FVREN FVRRDY
+ _
1.024V Fixed Reference
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Preliminary
DS41413A-page 131
PIC12F/LF1822/16F/LF1823
REGISTER 14-1:
R/W-0/0 FVREN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R-q/q R/W-0/0 Reserved R/W-0/0 Reserved R/W-0/0 CDAFVR1 R/W-0/0 CDAFVR0 R/W-0/0 ADFVR1 R/W-0/0 ADFVR0 bit 0
FVRRDY(1)
FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Reference is enabled FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not ready or not enabled 1 = Fixed Voltage Reference output is ready for use Reserved: Read as `0'. Maintain these bits clear. CDAFVR<1:0>: Comparator and DAC Fixed Voltage Reference Selection bits 00 = Comparator and DAC Fixed Voltage Reference Peripheral output is off 01 = Comparator and DAC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = Comparator and DAC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = Comparator and DAC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits 00 = ADC Fixed Voltage Reference Peripheral output is off 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) FVRRDY is always `1' on devices with the LDO (PIC12F1822/16F1823). Fixed Voltage Reference output cannot exceed VDD.
bit 6
bit 5-4 bit 3-2
bit 1-0
Note 1: 2:
TABLE 14-1:
Name FVRCON Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Bit 7 FVREN Bit 6 FVRRDY Bit 5 Reserved Bit 4 Reserved Bit 3 CDAFVR1 Bit 2 CDAFVR0 Bit 1 ADFVR1 Bit 0 ADFVR0 Register on page 132
Shaded cells are unused by the Fixed Voltage Reference module.
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PIC12F/LF1822/16F/LF1823
15.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep.
The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 15-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied.
FIGURE 15-1:
ADC BLOCK DIAGRAM
VDD ADPREF = 00 ADPREF = 11 VREF+ ADPREF = 10
AN0 AN1 AN2 AN3 AN4(2) AN5(2) AN6(2) AN7(2)
00000 00001 00010 00011 00100 00101 00110 00111 ADC GO/DONE 10 ADFM ADON(1) CHS<4:0> VSS ADRESH 0 = Left Justify 1 = Right Justify 16 ADRESL
DAC FVR Buffer1
11110 11111
Note 1: 2:
When ADON = 0, all multiplexer inputs are disconnected. Not available on PIC12F/LF1822.
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Preliminary
DS41413A-page 133
PIC12F/LF1822/16F/LF1823
15.1 ADC Configuration
15.1.4 CONVERSION CLOCK
When configuring and using the ADC the following functions must be considered: * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: * * * * * * * FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (dedicated internal oscillator)
15.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 12.0 "I/O Ports" for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.
The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 15-2. For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 29.0 "Electrical Specifications" for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
15.1.2
* * * *
CHANNEL SELECTION
There are up to 10 channel selections available: AN<3:0> pins (PIC12F/LF1822 only) AN<7:0> pins (PIC16F/LF1823 only) DAC Output FVR (Fixed Voltage Reference) Output
Refer to Section 16.0 "Digital-to-Analog Converter (DAC) Module" and Section 14.0 "Fixed Voltage Reference (FVR)" for more information on these channel selections. The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 15.2 "ADC Operation" for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: * VREF+ pin * VDD * FVR See Section 14.0 "Fixed Voltage Reference (FVR)" for more details on the fixed voltage reference.
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TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
Device Frequency (FOSC) Device Frequency (FOSC) 32 MHz 62.5ns(2) 125 ns
(2)
ADC Clock Period (TAD) ADC Clock Source Fosc/2 Fosc/4 Fosc/8 Fosc/16 Fosc/32 Fosc/64 FRC Legend: Note 1: 2: 3: 4: 5: ADCS<2:0> 000 100 001 101 010 110 x11 20 MHz 100 ns(2) 200 ns
(2)
16 MHz 125 ns(2) 250 ns
(2)
8 MHz 250 ns(2) 500 ns
(2)
4 MHz 500 ns(2) 1.0 s 2.0 s 4.0 s 8.0 s(3) 16.0 s(3)
(1,4)
1 MHz 2.0 s 4.0 s 8.0 s(3) 16.0 s(3) 32.0 s(3) 64.0 s(3) 1.0-6.0 s(1,4)
0.5 s(2) 800 ns 1.0 s 2.0 s 1.0-6.0 s
(1,4)
400 ns(2) 800 ns 1.6 s 3.2 s 1.0-6.0 s
(1,4)
0.5 s(2) 1.0 s 2.0 s 4.0 s 1.0-6.0 s
(1,4)
1.0 s 2.0 s 4.0 s 8.0 s(3)
(1,4)
1.0-6.0 s
1.0-6.0 s
Shaded cells are outside of recommended range. The FRC source has a typical TAD time of 1.6 s for VDD. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the conversion will be performed during Sleep. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
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Preliminary
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15.1.5 INTERRUPTS 15.1.6 RESULT FORMATTING
The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 8.0 "Interrupts" for more information. The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 15-3 shows the two output formats.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH ADRESL LSB bit 0 10-bit A/D Result bit 7 bit 0 Unimplemented: Read as `0' LSB bit 0 bit 7 10-bit A/D Result bit 0
(ADFM = 0)
MSB bit 7
(ADFM = 1) bit 7 Unimplemented: Read as `0'
MSB
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15.2
15.2.1
ADC Operation
STARTING A CONVERSION
15.2.4
ADC OPERATION DURING SLEEP
To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. Setting the GO/ DONE bit of the ADCON0 register to a `1' will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.6 "A/D Conversion Procedure".
The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC clock source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.
15.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will: * Clear the GO/DONE bit * Set the ADIF Interrupt Flag bit * Update the ADRESH and ADRESL registers with new conversion result
15.2.5
SPECIAL EVENT TRIGGER
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.
The Special Event Trigger of the CCP1 module allows periodic ADC measurements without software intervention. When this trigger occurs, the GO/DONE bit is set by hardware and the Timer1 counter resets to zero. Using the Special Event Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. Refer to Section 23.0 "Capture/Compare/PWM Modules" for more information.
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15.2.6 A/D CONVERSION PROCEDURE EXAMPLE 15-1: A/D CONVERSION
This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. Configure Port: * Disable pin output driver (Refer to the TRIS register) * Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt * Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: * Polling the GO/DONE bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 15.3 "A/D Acquisition Requirements".
;This code block configures the ADC ;for polling, Vdd and Vss references, Frc ;clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, Frc ;clock MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space
2.
3.
4. 5. 6.
7. 8.
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15.2.7 ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 15-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-2
ADCON0: A/D CONTROL REGISTER 0
R/W-0/0 CHS3 R/W-0/0 CHS2 R/W-0/0 CHS1 R/W-0/0 CHS0 R/W-0/0 GO/DONE R/W-0/0 ADON bit 0 CHS4
R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' CHS<4:0>: Analog Channel Select bits 00000 = AN0 00001 = AN1 00010 = AN2 00011 = AN3 00100 = AN4(1) 00101 = AN5(1) 00110 = AN6(1) 00111 = AN7(1) 01001 = Reserved. No channel connected. * * * 11101 = Reserved. No channel connected. 11110 = DAC output(2) 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3) GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current PIC16F/LF1823 only. For PIC12F/LF1822 it is "Reserved. No channel connected". See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information. See Section 14.0 "Fixed Voltage Reference (FVR)" for more information.
bit 1
bit 0
Note 1: 2: 3:
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REGISTER 15-2:
R/W-0/0 ADFM bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to `0' when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to `0' when the conversion result is loaded. ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock supplied from a dedicated RC oscillator) Unimplemented: Read as `0' ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits 00 = VREF+ is connected to AVDD 01 = Reserved 10 = VREF+ is connected to external VREF+ 11 = VREF+ is connected to internal fixed voltage reference U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADCON1: A/D CONTROL REGISTER 1
R/W-0/0 ADCS1 R/W-0/0 ADCS0 U-0 -- U-0 -- R/W-0/0 ADPREF1 R/W-0/0 ADPREF0 bit 0
R/W-0/0 ADCS2
bit 6-4
bit 3-2 bit 1-0
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REGISTER 15-3:
R/W-x/u ADRES9 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u ADRES7 R/W-x/u ADRES6 R/W-x/u ADRES5 R/W-x/u ADRES4 R/W-x/u ADRES3 R/W-x/u ADRES2 bit 0
R/W-x/u ADRES8
REGISTER 15-4:
R/W-x/u ADRES1 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 bit 5-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- bit 0
R/W-x/u ADRES0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result Reserved: Do not use.
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REGISTER 15-5:
R/W-x/u -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Reserved: Do not use. ADRES<9:8>: ADC Result Register bits Upper 2 bits of 10-bit conversion result U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u -- R/W-x/u ADRES9 R/W-x/u ADRES8 bit 0 --
R/W-x/u
REGISTER 15-6:
R/W-x/u ADRES7 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-0
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u ADRES5 R/W-x/u ADRES4 R/W-x/u ADRES3 R/W-x/u ADRES2 R/W-x/u ADRES1 R/W-x/u ADRES0 bit 0
R/W-x/u ADRES6
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADRES<7:0>: ADC Result Register bits Lower 8 bits of 10-bit conversion result
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15.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4. The maximum recommended impedance for analog sources is 10 k. As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 15-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
EQUATION 15-1: Assumptions:
ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V VDD
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF = 2s + TC + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations:
1 VAPPLIED 1 - -------------------------- = VCHOLD n+1 2 -1
--------- RC VAPPLIED 1 - e = VCHOLD - Tc - TC
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD charge response to VAPPLIED
-------- 1 RC VAPPLIED 1 - e = VAPPLIED 1 - -------------------------- ;combining [1] and [2] n+1 2 -1
Note: Where n = number of bits of the ADC. Solving for TC:
TC = - CHOLD RIC + RSS + RS ln(1/511) = - 10pF 1k + 7k + 10k ln(0.001957)
= 1.12 s Therefore: TACQ = 2s + 1.12s + [(50C - 25C) (0.05s/C)] = 4.42s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.
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FIGURE 15-4: ANALOG INPUT MODEL
VDD Rs VA ANx CPIN 5 pF VT 0.6V RIC 1k I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 10 pF VSS/VREF-
VT 0.6V
Legend: CHOLD CPIN
= Sample/Hold Capacitance = Input Capacitance
6V 5V VDD 4V 3V 2V
RSS
I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS VT = Sampling Switch = Threshold Voltage
5 6 7 8 9 10 11 Sampling Switch (k)
Note 1: Refer to Section 29.0 "Electrical Specifications".
FIGURE 15-5:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh FEh FDh ADC Output Code FCh FBh Full-Scale Transition 1 LSB ideal
04h 03h 02h 01h 00h 1 LSB ideal VSS Zero-Scale Transition VREF
Analog Input Voltage
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TABLE 15-2:
Name ADCON0 ADCON1 ADRESH ADRESL ANSELA ANSELC(1) CCP1CON DACCON0 DACCON1 FVRCON INTCON PIE1 PIR1 TRISA TRISC(1) Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7 -- ADFM Bit 6 CHS4 ADCS2 Bit 5 CHS3 ADCS1 Bit 4 CHS2 ADCS0 Bit 3 CHS1 -- Bit 2 CHS0 -- Bit 1 GO/DONE ADPREF1 Bit 0 ADON ADPREF0 Register on Page 139 140 141* 141* -- -- DC1B1 DACOE -- Reserved TMR0IE RCIE RCIF TRISA5 TRISC5 ANSA4 -- DC1B0 -- DACR4 Reserved INTE TXIE TXIF TRISA4 TRISC4 -- ANSC3 CCP1M3 DACPSS1 DACR3 CDAFVR1 IOCE SSP1IE SSP1IF TRISA3 TRISC3 ANSA2 ANSC2 CCP1M2 DACPSS0 DACR2 CDAFVR0 TMR0IF CCP1IE CCP1IF TRISA2 TRISC2 ANSA1 ANSC1 CCP1M1 -- DACR1 ADFVR1 INTF TMR2IE TMR2IF TRISA1 TRISC1 ANSA0 ANSC0 CCP1M0 -- DACR0 ADFVR0 IOCF TMR1IE TMR1IF TRISA0 TRISC0 122 126 221 151 151 132 89 90 92 121 125
A/D Result Register High A/D Result Register Low -- -- P1M1 DACEN -- FVREN GIE TMR1GIE TMR1GIF -- -- -- -- P1M0 DACLPS -- FVRRDY PEIE ADIE ADIF -- --
-- = unimplemented read as `0'. Shaded cells are not used for ADC module. Page provides register information. PIC16F/LF1823 only.
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NOTES:
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16.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE
16.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE
The DAC output voltage can be set to VSRC+ with the least amount of power consumption by performing the following: * Clearing the DACEN bit in the DACCON0 register. * Setting the DACLPS bit in the DACCON0 register. * Configuring the DACPSS bits to the proper positive source. * Configuring the DACR<4:0> bits to `11111' in the DACCON1 register. This is also the method used to output the voltage level from the FVR to an output pin. See Section 16.4 "DAC Voltage Reference Output" for more information. Reference Figure 16-1 for output clamping examples.
The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The input of the DAC can be connected to: * External VREF pins * VDD supply voltage * FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: * Comparator positive input * ADC input channel * DACOUT pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DACCON0 register.
16.3.2
OUTPUT CLAMPED TO NEGATIVE VOLTAGE SOURCE
16.1
Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register. The DAC output voltage is determined by the following equations:
The DAC output voltage can be set to VSRC- with the least amount of power consumption by performing the following: * Clearing the DACEN bit in the DACCON0 register. * Clearing the DACLPS bit in the DACCON0 register. * Configuring the DACNSS bits to the proper negative source. * Configuring the DACR<4:0> bits to `00000' in the DACCON1 register. This allows the comparator to detect a zero-crossing while not consuming additional current through the DAC module. Reference Figure 16-1 for output clamping examples.
EQUATION 16-1:
DAC OUTPUT VOLTAGE
2
DACR<4:0> VOUT = VSOURCE+ - VSOURCE- ------------------------------ + VSRC- 5 Note: VSOURCE+ can equal FVR Buffer 2, VDD or VREF+. VSOURCE- can equal VSS or VREF-.
16.2
Ratiometric Output Level
The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Section 29.0 "Electrical Specifications".
16.3
Low-Power Voltage State
In order for the DAC module to consume the least amount of power, one of the two voltage reference input sources to the resistor ladder must be disconnected. Either the positive voltage source, (VSRC+), or the negative voltage source, (VSRC-) can be disabled. The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source.
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FIGURE 16-1: OUTPUT VOLTAGE CLAMPING EXAMPLES
Output Clamped to Positive Voltage Source VSRC+ R R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see Figure 16-2) R VSRCVSRCDACEN = 0 DACLPS = 0 DACR<4:0> = 11111 R R DAC Voltage Ladder (see Figure 16-2) R DACR<4:0> = 00000 Output Clamped to Positive Voltage Source VSRC+
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16.4 DAC Voltage Reference Output
The DAC can be output to the DACOUT pin by setting the DACOE bit of the DACCON0 register to `1'. Selecting the DAC reference voltage for output on the DACOUT pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a `0'. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT. Figure 16-3 shows an example buffering technique.
FIGURE 16-2:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC) FVR BUFFER2 VDD VREF+
VSRC+
5 R R 2 R R 32 Steps R R R 32-to-1 MUX R
DACR<4:0>
DACPSS<1:0> DACEN DACLPS
DAC (To Comparator, CSM and ADC Modules)
DACOUT DACOE
VREFVSS
VSRC-
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PIC12F/LF1822/16F/LF1823
FIGURE 16-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC(R) MCU
DAC Module
R Voltage Reference Output Impedance DACOUT
+ -
Buffered DAC Output
16.5
Operation During Sleep
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DACCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
16.6
Effects of a Reset
A device Reset affects the following: * DAC is disabled. * DAC output voltage is removed from the DACOUT pin. * The DACR<4:0> range select bits are cleared.
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REGISTER 16-1:
R/W-0/0 DACEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared DACEN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled DACLPS: DAC Low-Power Voltage State Select bit 1 = DAC Positive reference source selected 0 = DAC Negative reference source selected DACOE: DAC Voltage Output Enable bit 1 = DAC voltage level is also an output on the DACOUT pin 0 = DAC voltage level is disconnected from the DACOUT pin Unimplemented: Read as `0' DACPSS<1:0>: DAC Positive Source Select bits 00 = VDD 01 = VREF+ 10 = FVR Buffer2 output 11 = Reserved, do not use Unimplemented: Read as `0' U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 DACOE U-0 -- R/W-0/0 R/W-0/0 U-0 -- U-0 -- bit 0 DACPSS<1:0>
R/W-0/0 DACLPS
bit 6
bit 5
bit 4 bit 3-2
bit 1-0
REGISTER 16-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4-0 Note 1:
DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 DACR<4:0> bit 0 R/W-0/0 R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25)) + VSRCThe output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout.
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TABLE 16-1:
Name FVRCON DACCON0 DACCON1 Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Bit 7 FVREN DACEN -- Bit 6 FVRRDY DACLPS -- Bit 5 Reserved DACOE -- Bit 4 Reserved -- DACR4 Bit 3 CDAFVR1 DACPSS1 DACR3 Bit 2 CDAFVR0 DACPSS0 DACR2 Bit 1 ADFVR1 -- DACR1 Bit 0 ADFVR0 -- DACR0 Register on page 132 151 151
-- = unimplemented, read as `0'. Shaded cells are unused by the DAC module.
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17.0 SR LATCH
17.2 Latch Output
The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: * * * * Programmable input selection SR Latch output is available externally Separate Q and Q outputs Firmware Set and Reset The SRQEN and SRNQEN bits of the SRCON0 register control the Q and Q latch outputs. Both of the SR Latch outputs may be directly output to an I/O pin at the same time. The applicable TRIS bit of the corresponding port must be cleared to enable the port pin output driver.
The SR Latch can be used in a variety of analog applications, including oscillator circuits, one-shot circuit, hysteretic controllers, and analog timing applications.
17.3
Effects of a Reset
17.1
Latch Operation
Upon any device Reset, the SR Latch output is not initialized to a known state. The user's firmware is responsible for initializing the latch output before enabling the output pins.
The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high. The latch can be Set or Reset by: * Software control (SRPS and SRPR bits) * Comparator C1 output (SYNCC1OUT) * Comparator C2 output (SYNCC2OUT) (PIC16F/LF1823 only) * SRI pin * Programmable clock (SRCLK) The SRPS and the SRPR bits of the SRCON0 register may be used to Set or Reset the SR Latch, respectively. The latch is Reset-dominant. Therefore, if both Set and Reset inputs are high, the latch will go to the Reset state. Both the SRPS and SRPR bits are self resetting which means that a single write to either of the bits is all that is necessary to complete a latch Set or Reset operation. The output from Comparator C1 or C2 can be used as the Set or Reset inputs of the SR Latch. The output of either Comparator can be synchronized to the Timer1 clock source. See Section 18.0 "Comparator Module" and Section 20.0 "Timer1 Module with Gate Control" for more information. An external source on the SRI pin can be used as the Set or Reset inputs of the SR Latch. An internal clock source is available that can periodically set or reset the SR Latch. The SRCLK<2:0> bits in the SRCON0 register are used to select the clock source period. The SRSCKE and SRRCKE bits of the SRCON1 register enable the clock source to Set or Reset the SR Latch, respectively. Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured.
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FIGURE 17-1:
SRPS
SR LATCH SIMPLIFIED BLOCK DIAGRAM
Pulse Gen(2) SRLEN SRQEN
SRI SRSPE SRCLK SRSCKE SYNCC2OUT(3, 4) SRSC2E(4) SYNCC1OUT(3) SRSC1E SRPR Pulse Gen(2) SR Latch(1) S Q SRQ
SRI SRRPE SRCLK SRRCKE SYNCC2OUT(3, 4) SRRC2E(4) SYNCC1OUT(3) SRRC1E R Q SRNQ SRLEN SRNQEN
Note 1: 2: 3: 4:
If R = 1 and S = 1 simultaneously, Q = 0, Q = 1 Pulse generator causes a 1 Q-state pulse width. Name denotes the connection point at the comparator output. PIC16F/LF1823 only.
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TABLE 17-1:
SRCLK 111 110 101 100 011 010 001 000
SRCLK FREQUENCY TABLE
Divider 512 256 128 64 32 16 8 4 FOSC = 32 MHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC = 20 MHz 39.0 kHz 78.1 kHz 156 kHz 313 kHz 625 kHz 1.25 MHz 2.5 MHz 5 MHz FOSC = 16 MHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz FOSC = 4 MHz 7.81 kHz 15.6 kHz 31.25 kHz 62.5 kHz 125 kHz 250 kHz 500 kHz 1 MHz FOSC = 1 MHz 1.95 kHz 3.90 kHz 7.81 kHz 15.6 kHz 31.3 kHz 62.5 kHz 125 kHz 250 kHz
REGISTER 17-1:
R/W-0/0 SRLEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
SRCON0: SR LATCH CONTROL 0 REGISTER
R/W-0/0 SRCLK1 R/W-0/0 SRCLK0 R/W-0/0 SRQEN R/W-0/0 SRNQEN R/S-0/0 SRPS R/S-0/0 SRPR bit 0
R/W-0/0 SRCLK2
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets S = Bit is set only
SRLEN: SR Latch Enable bit 1 = SR Latch is enabled 0 = SR Latch is disabled SRCLK<2:0>: SR Latch Clock Divider bits 000 = Generates a 1 FOSC wide pulse every 4th FOSC cycle clock 001 = Generates a 1 FOSC wide pulse every 8th FOSC cycle clock 010 = Generates a 1 FOSC wide pulse every 16th FOSC cycle clock 011 = Generates a 1 FOSC wide pulse every 32nd FOSC cycle clock 100 = Generates a 1 FOSC wide pulse every 64th FOSC cycle clock 101 = Generates a 1 FOSC wide pulse every 128th FOSC cycle clock 110 = Generates a 1 FOSC wide pulse every 256th FOSC cycle clock 111 = Generates a 1 FOSC wide pulse every 512th FOSC cycle clock SRQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled SRNQEN: SR Latch Q Output Enable bit If SRLEN = 1: 1 = Q is present on the SRnQ pin 0 = External Q output is disabled If SRLEN = 0: SR Latch is disabled SRPS: Pulse Set Input of the SR Latch bit(1) 1 = Pulse set input for 1 Q-clock period 0 = No effect on set input. SRPR: Pulse Reset Input of the SR Latch bit(1) 1 = Pulse reset input for 1 Q-clock period 0 = No effect on reset input. Set only, always reads back `0'.
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 17-2:
R/W-0/0 SRSPE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SRSPE: SR Latch Peripheral Set Enable bit 1 = SR Latch is set when the SRI pin is high 0 = SRI pin has no effect on the set input of the SR Latch SRSCKE: SR Latch Set Clock Enable bit 1 = Set input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the set input of the SR Latch SRSC2E: SR Latch C2 Set Enable bit(1) 1 = SR Latch is set when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the set input of the SR Latch SRSC1E: SR Latch C1 Set Enable bit 1 = SR Latch is set when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the set input of the SR Latch SRRPE: SR Latch Peripheral Reset Enable bit 1 = SR Latch is reset when the SRI pin is high 0 = SRI pin has no effect on the reset input of the SR Latch SRRCKE: SR Latch Reset Clock Enable bit 1 = Reset input of SR Latch is pulsed with SRCLK 0 = SRCLK has no effect on the reset input of the SR Latch SRRC2E: SR Latch C2 Reset Enable bit(1) 1 = SR Latch is reset when the C2 Comparator output is high 0 = C2 Comparator output has no effect on the reset input of the SR Latch SRRC1E: SR Latch C1 Reset Enable bit 1 = SR Latch is reset when the C1 Comparator output is high 0 = C1 Comparator output has no effect on the reset input of the SR Latch PIC16F/LF1823 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SRCON1: SR LATCH CONTROL 1 REGISTER
R/W-0/0 SRSC2E(1) R/W-0/0 SRSC1E R/W-0/0 SRRPE R/W-0/0 SRRCKE R/W-0/0 SRRC2E(1) R/W-0/0 SRRC1E bit 0
R/W-0/0 SRSCKE
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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TABLE 17-2:
Name ANSELA SRCON0 SRCON1 TRISA Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SR LATCH MODULE
Bit 7 -- SRLEN SRSPE -- Bit 6 -- SRCLK2 SRSCKE -- Bit 5 -- SRCLK1 SRSC2E(1) TRISA5 Bit 4 ANSA4 SRCLK0 SRSC1E TRISA4 Bit 3 ANSA3 SRQEN SRRPE TRISA3 Bit 2 ANSA2 SRNQEN SRRCKE TRISA2 Bit 1 ANSA1 SRPS SRRC2E(1) TRISA1 Bit 0 ANSA0 SRPR SRRC1E TRISA0 Register on Page 122 155 156 121
-- = unimplemented, read as `0'. Shaded cells are unused by the SR Latch module. PIC16F/LF1823 only.
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NOTES:
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18.0 COMPARATOR MODULE
FIGURE 18-1:
VIN+ VIN-
SINGLE COMPARATOR
+ - Output
Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: * * * * * * * * * Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and fixed voltage reference
VINVIN+
Output
Note:
18.1
Comparator Overview
The black areas of the output of the comparator represents the uncertainty due to input offsets and response time.
A single comparator is shown in Figure 18-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The PIC12F/LF1822 devices contain one comparator, while the PIC16F/LF1823 devices contain two.
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PIC12F/LF1822/16F/LF1823
FIGURE 18-2:
CxNCH<1:0> 2
COMPARATOR 1 MODULE SIMPLIFIED BLOCK DIAGRAM (PIC12F/LF1822)
C1ON(1)
Interrupt det
C1INTP
C1IN0-
Set C1IF 0 MUX
(2)
Interrupt det
C1POL C1VN
C1INTN
C1IN1-
1
Cx(3) D Q
C1OUT MC1OUT
To Data Bus
C1VP C1IN+ DAC FVR Buffer2 0 MUX 1 (2) 2 3 VSS C1PCH<1:0> 2
+
Q1 C1HYS C1SP To ECCP PWM Logic EN
C1ON
C1SYNC
C1OE
TRIS bit C1OUT
0 D (from Timer1) T1CLK Q 1
To Timer1 or SR Latch SYNCC1OUT
Note
1: 2: 3:
When C1ON = 0, the Comparator will produce a `0' at the output. When C1ON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging.
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FIGURE 18-3:
CxNCH<1:0> 2 C12IN0C12IN1C12IN2C12IN30 1 MUX 2 (2) 3 CXPOL CxVN
COMPARATOR 1 AND 2 MODULES SIMPLIFIED BLOCK DIAGRAM (PIC16F/LF1823)
CxON(1)
Interrupt det
CxINTP
Set CxIF
Interrupt det
CxINTN
Cx(3) D Q
CXOUT MCXOUT
To Data Bus
CxVP CXIN+ DAC FVR Buffer2 0 MUX 1 (2) 2 3 VSS CXPCH<1:0> 2
+
Q1 CxHYS CxSP To ECCP PWM Logic EN
CxON
CXSYNC
CXOE
TRIS bit CXOUT
0 D (from Timer1) T1CLK Q 1
To Timer1 or SR Latch SYNCCXOUT
Note
1: 2: 3:
When CxON = 0, the Comparator will produce a `0' at the output. When CxON = 0, all multiplexer inputs are disconnected. Output of comparator can be frozen during debugging.
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18.2 Comparator Control
18.2.3 COMPARATOR OUTPUT POLARITY
Each comparator has 2 control registers: CMxCON0 and CMxCON1. The CMxCON0 registers (see Register 18-1) contain Control and Status bits for the following: * * * * * * Enable Output selection Output polarity Speed/Power selection Hysteresis enable Output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 18-1 shows the output state versus input conditions, including polarity control.
TABLE 18-1:
COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS
CxPOL 0 0 1 1 CxOUT 0 1 0 1
Input Condition CxVN > CxVP CxVN < CxVP CxVN > CxVP CxVN < CxVP
The CMxCON1 registers (see Register 18-2) contain Control bits for the following: * * * * Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection
18.2.4
18.2.1
COMPARATOR ENABLE
COMPARATOR SPEED/POWER SELECTION
Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption.
18.2.2
COMPARATOR OUTPUT SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is `1' which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to `0'.
The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: * CxOE bit of the CMxCON0 register must be set * Corresponding TRIS bit must be cleared * CxON bit of the CMxCON0 register must be set Note 1: The CxOE bit of the CMxCON0 register overrides the PORT data latch. Setting the CxON bit of the CMxCON0 register has no impact on the port override. 2: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched.
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18.3 Comparator Hysteresis 18.5 Comparator Interrupt
A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. These hysteresis levels change as a function of the comparator's Speed/Power mode selection. Table 18-2 shows the hysteresis levels. An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: * CxON, CxPOL and CxSP bits of the CMxCON0 register * CxIE bit of the PIE2 register * CxINTP bit of the CMxCON1 register (for a rising edge detection) * CxINTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register.
TABLE 18-2:
CxSP 0 1
HYSTERESIS LEVELS
CxHYS Enabled 3mV 20mV CxHYS Disabled << 1mV 3mV
These levels are approximate. See Section 29.0 "Electrical Specifications" for more information.
18.4
Timer1 Gate Operation
The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 20.6 "Timer1 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring.
18.6
18.4.1
COMPARATOR OUTPUT SYNCHRONIZATION
Comparator Positive Input Selection
The output from either comparator, C1 or C2, can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure ) and the Timer1 Block Diagram (Figure 20-1) for more information.
Configuring the CxPCH<1:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * C1IN+ or C2IN+ analog pin DAC FVR (Fixed Voltage Reference) VSS (Ground)
See Section 14.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled.
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18.7 Comparator Negative Input Selection 18.10 Analog Input Connection Considerations
A simplified circuit for an analog input is shown in Figure 18-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
The CxNCH<1:0> bits of the CMxCON0 register direct one of the analog pins to the comparator inverting input. Note: To use CxIN+ and CxINx- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers.
18.8
Comparator Response Time
The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Section 29.0 "Electrical Specifications" for more details.
18.9
Interaction with ECCP Logic
The C1 and C2 comparators can be used as general purpose comparators. Their outputs can be brought out to the C1OUT and C2OUT pins. When the ECCP Auto-Shutdown is active it can use one or both comparators. If auto-restart is also enabled, the comparators can be configured as a closed loop analog feedback to the ECCP, thereby, creating an analog controlled PWM.
FIGURE 18-4:
ANALOG INPUT MODEL
VDD Analog Input pin
Rs < 10K
VT 0.6V
RIC To Comparator
VA
CPIN 5 pF
VT 0.6V
ILEAKAGE(1)
Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Source Impedance RS = Analog Voltage VA VT = Threshold Voltage
Note 1: See Section 29.0 "Electrical Specifications".
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REGISTER 18-1:
R/W-0/0 CxON bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxON: Comparator Enable bit 1 = Comparator is enabled and consumes no active power 0 = Comparator is disabled CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN CxOE: Comparator Output Enable bit 1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually drive the pin. Not affected by CxON. 0 = CxOUT is internal only CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as `0' CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in normal power, higher speed mode 0 = Comparator operates in low-power, low-speed mode CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CMxCON0: COMPARATOR X CONTROL REGISTER 0
R-0/0 R/W-0/0 CxOE R/W-0/0 CxPOL U-0 -- R/W-1/1 CxSP R/W-0/0 CxHYS R/W-0/0 CxSYNC bit 0
CxOUT
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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REGISTER 18-2:
R/W-0/0 CxINTP bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit CxPCH<1:0>: Comparator Positive Input Channel Select bits 00 = CxVP connects to CxIN+ pin 01 = CxVP connects to DAC Voltage Reference 10 = CxVP connects to FVR Voltage Reference Unimplemented: Read as `0' CxNCH<1:0>: Comparator Negative Input Channel Select bits PIC12F/LF1822: 0 = C1VN connects to C1IN0- pin 1 = C1VN connects to C1IN1- pin PIC16F/LF1823: 00 = CxVN connects to C12IN0- pin 01 = CxVN connects to C12IN1- pin 10 = CxVN connects to C12IN2- pin 11 = CxVN connects to C12IN3- pin Note 1: PIC16F/LF1823 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CMxCON1: COMPARATOR CX CONTROL REGISTER 1
R/W-0/0 R/W-0/0 U-0 -- U-0 -- R/W-0/0 CxNCH1
(1)
R/W-0/0 CxINTN
R/W-0/0 CxNCH0 bit 0
CxPCH<1:0>
bit 6
bit 5-4
bit 3-2 bit 1-0
REGISTER 18-3:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-2 bit 1 bit 0 Note 1:
CMOUT: COMPARATOR OUTPUT REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R-0/0 MC2OUT(1) R-0/0 MC1OUT bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
Unimplemented: Read as `0' MC2OUT: Mirror Copy of C2OUT bit(1) MC1OUT: Mirror Copy of C1OUT bit PIC16F/LF1823 only.
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TABLE 18-3:
Name ANSELA CM1CON0 CM1CON1 CM2CON0(1) CM2CON1(1) CMOUT INTCON PIE2 PIR2 TRISA TRISC(1) Legend: Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 -- C1ON C1INTP C2ON C2INTP -- GIE OSFIE OSFIF -- -- Bit 6 -- C1OUT C1INTN C2OUT C2INTN -- PEIE C2IE(1) C2IF(1) -- -- Bit 5 -- C1OE C1PCH1 C2OE C2PCH1 -- TMR0IE C1IE C1IF TRISA5 TRISC5 Bit 4 ANSA4 C1POL C1PCH0 C2POL C2PCH0 -- INTE EEIE EEIF TRISA4 TRISC4 Bit 3 ANSA3 -- -- -- -- -- IOCIE BCL1IE BCL1IF TRISA3 TRISC3 Bit 2 ANSA2 C1SP -- C2SP -- -- TMR0IF -- -- TRISA2 TRISC2 Bit 1 ANSA1 C1HYS -- C2HYS C2NCH1 MC2OUT INTF -- -- TRISA1 TRISC1
(1)
Bit 0 ANSA0 C1SYNC C1NCH0 C2SYNC C2NCH0 MC1OUT IOCIF -- -- TRISA0 TRISC0
Register on Page 122 165 166 165 166 166 89 91 93 121 125
-- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. PIC16F/LF1823 only.
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NOTES:
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PIC12F/LF1822/16F/LF1823
19.0 TIMER0 MODULE
19.1.2 8-BIT COUNTER MODE
The Timer0 module is an 8-bit timer/counter with the following features: * * * * * * 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 In 8-bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to `1' and resetting the T0XCS bit in the CPSCON0 register to `0'. 8-Bit Counter mode using the Capacitive Sensing Oscillator (CPSCLK) signal is selected by setting the TMR0CS bit in the OPTION register to `1' and setting the T0XCS bit in the CPSCON0 register to `1'. The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION register.
Figure 19-1 is a block diagram of the Timer0 module.
19.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer or an 8-bit counter.
19.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written.
FIGURE 19-1:
FOSC/4
BLOCK DIAGRAM OF THE TIMER0
Data Bus 0 T0CKI 0 From CPSCLK 1 0 1 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 1 Sync 2 TCY 8 TMR0
T0XCS
8
PS<2:0>
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PIC12F/LF1822/16F/LF1823
19.1.3 SOFTWARE PROGRAMMABLE PRESCALER
A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION register. Note: The Watchdog Timer (WDT) uses its own independent prescaler.
There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler.
19.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION
19.1.5
When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Section 29.0 "Electrical Specifications".
19.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.
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REGISTER 19-1:
R/W-1/1 WPUEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RA2/INT pin 0 = Interrupt on falling edge of RA2/INT pin TMR0CS: Timer0 Clock Source Select bit 1 = Transition on RA2/T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on RA2/T0CKI pin 0 = Increment on low-to-high transition on RA2/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
OPTION_REG: OPTION REGISTER
R/W-1/1 TMR0CS R/W-1/1 TMR0SE R/W-1/1 PSA R/W-1/1 R/W-1/1 PS<2:0> bit 0 R/W-1/1
R/W-1/1 INTEDG
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 19-1:
Name CPSCON0 INTCON TMR0 TRISA
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7 CPSON GIE Bit 6 CPSRM PEIE Bit 5 -- TMR0IE Bit 4 -- INTE Bit 3 Bit 2 Bit 1 Bit 0 T0XCS IOCIF PS0 TRISA0 Register on Page 313 89 171 169* TRISA4 TRISA3 TRISA2 TRISA1 121
CPSRNG1 CPSRNG0 CPSOUT IOCIE PSA TMR0IF PS2 INTF PS1
OPTION_REG WPUEN --
INTEDG TMR0CS TMR0SE -- TRISA5
Timer0 Module Register
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the Timer0 module. * Page provides register information.
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20.0 TIMER1 MODULE WITH GATE CONTROL
* * * * Gate Toggle Mode Gate Single-pulse Mode Gate Value Status Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the following features: * * * * * * * * 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) * Time base for the Capture/Compare function * Special Event Trigger (with CCP/ECCP) * Selectable Gate Source Polarity
Figure 20-1 is a block diagram of the Timer1 module.
FIGURE 20-1:
T1GSS<1:0> T1G
TIMER1 BLOCK DIAGRAM
00 01 10 D 11 TMR1ON T1GPOL Set flag bit TMR1IF on Overflow T1GTM CK R Q Q 1 T1G_IN
T1GSPM 0 0 Single Pulse Acq. Control T1GGO/DONE 1 Data Bus D EN Q RD T1GCON Set TMR1GIF
From Timer0 Overflow Comparator 1 SYNCC1OUT Comparator 2 SYNCC2OUT
T1GVAL Q1
Interrupt det TMR1GE TMR1ON
TMR1(2) TMR1H TMR1L Q
To Comparator Module EN D T1CLK 0 1 TMR1CS<1:0> Synchronized clock input
T1OSO
T1SYNC 11 10 Synchronize(3) det
OUT T1OSC 1
Cap. Sensing Oscillator
T1OSI
Prescaler 1, 2, 4, 8 2 T1CKPS<1:0> FOSC/2 Internal Clock
EN 0 FOSC Internal Clock FOSC/4 Internal Clock
01
T1OSCEN
(1)
Sleep input
00
T1CKI To Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep.
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20.1 Timer1 Operation 20.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 20-1 displays the Timer1 enable selections. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 20-2 displays the clock source selections.
20.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: * Asynchronous event on the T1G pin to Timer1 Gate * C1 or C2 comparator input to Timer1 Gate
TABLE 20-1:
TMR1ON 0 0 1 1
TIMER1 ENABLE SELECTIONS
TMR1GE 0 1 0 1 Timer1 Operation Off Off Always On Count Enabled
20.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low.
TABLE 20-2:
TMR1CS1 0 0 1 1 1
CLOCK SOURCE SELECTIONS
TMR1CS0 1 0 1 0 0 T1OSCEN x x x 0 1 System Clock (FOSC) Instruction Clock (FOSC/4) Capacitive Sensing Oscillator External Clocking on T1CKI Pin Osc.Circuit On T1OSI/T1OSO Pins Clock Source
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20.3 Timer1 Prescaler 20.6 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 Gate can also be driven by multiple selectable sources.
20.4
Timer1 Oscillator
20.6.1
TIMER1 GATE ENABLE
A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.
The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 20-3 for timing details.
TABLE 20-3:
T1CLK
TIMER1 GATE ENABLE SELECTIONS
T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts 0 0 1 1
20.5
Timer1 Operation in Asynchronous Counter Mode
T1GPOL
If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 20.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.
20.6.2
TIMER1 GATE SOURCE SELECTION
The Timer1 Gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register.
TABLE 20-4:
T1GSS 00 01 10 11
TIMER1 GATE SOURCES
Timer1 Gate Source
Timer1 Gate Pin Overflow of Timer0 (TMR0 increments from FFh to 00h) Comparator 1 Output SYNCC1OUT (optionally Timer1 synchronized output) Comparator 2 Output SYNCC2OUT (optionally Timer1 synchronized output)
20.5.1
READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.
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20.6.2.1 T1G Pin Gate Operation 20.6.4
The T1G pin is one source for Timer1 Gate Control. It can be used to supply an external source to the Timer1 Gate circuitry.
TIMER1 GATE SINGLE-PULSE MODE
20.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 Gate circuitry.
20.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can be selected as a source for Timer1 Gate Control. The Comparator 1 output (SYNCC1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 18.4.1 "Comparator Output Synchronization".
When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/DONE bit. See Figure 20-5 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 Gate source to be measured. See Figure 20-6 for timing details.
20.6.2.4
Comparator C2 Gate Operation (PIC16F/LF1823)
The output resulting from a Comparator 2 operation can be selected as a source for Timer1 Gate Control. The Comparator 2 output (SYNCC2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 18.4.1 "Comparator Output Synchronization".
20.6.5
TIMER1 GATE VALUE STATUS
20.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 Gate is not enabled (TMR1GE bit is cleared).
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 Gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 20-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
20.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared).
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20.7 Timer1 Interrupt 20.9
The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: * * * * TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register
ECCP/CCP Capture/Compare Time Base
The CCP1 module uses the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be a Special Event Trigger. For more information, see "Capture/Compare/PWM Modules". Section 23.0
The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts.
20.10 ECCP/CCP Special Event Trigger
When any of the CCP's are configured to trigger a special event, the trigger will clear the TMR1H:TMR1L register pair. This special event does not cause a Timer1 interrupt. The CCP1 module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with a Special Event Trigger from the CCP, the write will take precedence. For more information, see Section 15.2.5 "Special Event Trigger".
20.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured * T1OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting.
FIGURE 20-2:
T1CKI = 1 when TMR1 Enabled
TIMER1 INCREMENTING EDGE
T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
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FIGURE 20-3: TIMER1 GATE ENABLE MODE
TMR1GE T1GPOL T1G_IN
T1CKI
T1GVAL
Timer1
N
N+1
N+2
N+3
N+4
FIGURE 20-4:
TIMER1 GATE TOGGLE MODE
TMR1GE T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7
N+8
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FIGURE 20-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE T1GPOL T1GSPM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
T1CKI
T1GVAL
Timer1
N
N+1
N+2 Set by hardware on falling edge of T1GVAL Cleared by software
TMR1GIF
Cleared by software
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FIGURE 20-6:
TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ DONE T1G_IN Set by software Counting enabled on rising edge of T1G Cleared by hardware on falling edge of T1GVAL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1CKI
T1GVAL
Timer1
N
N+1
N+2
N+3
N+4 Cleared by software
TMR1GIF
Cleared by software
Set by hardware on falling edge of T1GVAL
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20.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in Register 20-1, is used to control Timer1 and select the various features of the Timer1 module.
REGISTER 20-1:
R/W-0/u bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u T1OSCEN R/W-0/u T1SYNC U-0 -- R/W-0/u TMR1ON bit 0
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on T1OSI/T1OSO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated Timer1 oscillator circuit enabled 0 = Dedicated Timer1 oscillator circuit disabled T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS<1:0> = 1X 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock (FOSC) TMR1CS<1:0> = 0X This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 5-4
bit 3
bit 2
bit 1 bit 0
Unimplemented: Read as `0' TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop
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20.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in Register 20-2, is used to control Timer1 Gate.
REGISTER 20-2:
R/W-0/u TMR1GE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u T1GTM R/W-0/u T1GSPM R/W/HC-0/u T1GGO/ DONE R-x/x T1GVAL R/W-0/u R/W-0/u
R/W-0/u T1GPOL
T1GSS<1:0> bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware
TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 gate Single-Pulse mode is disabled T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected by Timer1 Gate Enable (TMR1GE). T1GSS<1:0>: Timer1 Gate Source Select bits 00 = Timer1 Gate pin 01 = Timer0 overflow output 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) 11 = Comparator 2 optionally synchronized output (SYNCC2OUT)(1) PIC16F/LF1823 only.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Note 1:
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TABLE 20-5:
Name ANSELA CCP1CON INTCON PIE1 PIR1 TMR1H TMR1L TRISA T1CON T1GCON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Bit 7 -- P1M1 GIE Bit 6 -- P1M0 PEIE ADIE ADIF Bit 5 -- DC1B1 TMR0IE RCIE RCIF Bit 4 ANSA4 DC1B0 INTE TXIE TXIF Bit 3 -- CCP1M3 IOCIE SSP1IE SSP1IF Bit 2 ANSA2 TMR0IF CCP1IE CCP1IF Bit 1 ANSA1 INTF TMR2IE TMR2IF Bit 0 ANSA0 IOCIF TMR1IE TMR1IF Register on Page 122 221 89 90 92 172* 172* TRISA0 TMR1ON T1GSS0 121 180 181 -- T1GSS1
CCP1M2 CCP1M1 CCP1M0
TMR1GIE TMR1GIF
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register -- TMR1GE -- T1GPOL TRISA5 T1GTM TRISA4 T1GSPM TRISA3 T1GGO/ DONE TRISA2 T1GVAL TRISA1 TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. * Page provides register information. Note 1: PIC16F/LF1823 only.
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21.0 TIMER2 MODULE
The Timer2 module incorporate the following features: * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMR2 match with PR2, respectively * Optional use as the shift clock for the MSSP1 modules (Timer2 only) See Figure 21-1 for a block diagram of Timer2.
FIGURE 21-1:
TIMER2 BLOCK DIAGRAM
TMRx Outp2t Sets Flag bit TMR2IF
FOSC/4
Prescaler 1:1, 1:4, 1:16, 1:64 2 T2CKPS<1:0>
TMR2 Comparator
Reset Postscaler 1:1 to 1:16 4 T2OUTPS<3:0>
EQ
PR2
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21.1 Timer2 Operation 21.3 Timer2 Output
The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 21.2 "Timer2 Interrupt"). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: TMR2 is not cleared when T2CON is written. The unscaled output of TMR2 is available primarily to the CCP1 module, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP1 module operating in SPI mode. Additional information is provided in Section 24.1 "Master SSP (MSSP1) Module Overview"
21.4
Timer2 Operation During Sleep
The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode.
21.2
Timer2 Interrupt
Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register.
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REGISTER 21-1:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 bit 6-3 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' TOUTPS<3:0>: Timer Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscaler 0100 = 1:5 Postscaler 0101 = 1:6 Postscaler 0110 = 1:7 Postscaler 0111 = 1:8 Postscaler 1000 = 1:9 Postscaler 1001 = 1:10 Postscaler 1010 = 1:11 Postscaler 1011 = 1:12 Postscaler 1100 = 1:13 Postscaler 1101 = 1:14 Postscaler 1110 = 1:15 Postscaler 1111 = 1:16 Postscaler TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 11 = Prescaler is 64 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR2ON R/W-0/0 R/W-0/0 bit 0 TOUTPS<3:0> T2CKPS<1:0>
R/W-0/0
bit 2
bit 1-0
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TABLE 21-1:
Name CCP1CON INTCON PIE1 PIR1 PR2 T2CON TMR2
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 221 IOCIF TMR1IE TMR1IF 89 90 92 184* TMR2ON T2CKPS1 T2CKPS0 186 184*
P1M<1:0> GIE TMR1GIE TMR1GIF -- PEIE ADIE ADIF
DC1B<1:0> TMR0IE RCIE RCIF INTE TXIE TXIF IOCIE SSPIE SSPIF
CCP1M<3:0> TMR0IF CCP1IE CCP1IF INTF TMR2IE TMR2IF
Timer2 Module Period Register TOUTPS<3:0> Holding Register for the 8-bit TMR2 Register
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2 module. * Page provides register information.
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NOTES:
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22.0 DATA SIGNAL MODULATOR
The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * * * Carrier Synchronization Carrier Source Polarity Select Carrier Source Pin Disable Programmable Modulator Data Modulator Source Pin Disable Modulated Output Polarity Select Slew Rate Control
Figure 22-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral.
FIGURE 22-1:
MDCH<3:0> VSS MDCIN1 MDCIN2 CLKR CCP1 Reserved No Channel Selected
SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR
0000 0001 0010 0011 0100 0101 CARH 0110 * * * * 1111 MDEN EN Data Signal Modulator
MDCHPOL D SYNC Q 1
MDMS<3:0> MDBIT MDMIN CCP1 Reserved No Channel Selected Comparator C1 Comparator C2(1) MSSP1 SDO1 Reserved EUSART Reserved No Channel Selected 0000 0001 0010 0011 * 0101 0110 MOD 0111 1000 1001 1010 0011 * * 1111 D MDCL<3:0> VSS MDCIN1 MDCIN2 CLKR CCP1 Reserved No Channel Selected 0000 0001 0010 0011 0100 0101 CARL 0110 0111 1000 * * 1111 SYNC
0 MDCHSYNC MDOUT MDOPOL MDOE
Q
1
0 MDCLSYNC
MDCLPOL
Note
1:
PIC16F/LF1823 only.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 189
PIC12F/LF1822/16F/LF1823
22.1 DSM Operation 22.3 Carrier Signal Sources
The DSM module can be enabled by setting the MDEN bit in the MDCON register. Clearing the MDEN bit in the MDCON register, disables the DSM module by automatically switching the carrier high and carrier low signals to the VSS signal source. The modulator signal source is also switched to the MDBIT in the MDCON register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low, and modulator sources held by the Modulation Source, Modulation High Carrier, and Modulation Low Carrier control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the MDEN bit is set and the DSM module is again enabled and active. The modulated output signal can be disabled without shutting down the DSM module. The DSM module will remain active and continue to mix signals, but the output value will not be sent to the MDOUT pin. During the time that the output is disabled, the MDOUT pin will remain low. The modulated output can be disabled by clearing the MDOE bit in the MDCON register. The carrier high signal and carrier low signal can be supplied from the following sources: * * * * * CCP1 Signal Reference Clock Module Signal External Signal on MDCIN1 pin External Signal on MDCIN2 pin VSS
The carrier high signal is selected by configuring the MDCH <3:0> bits in the MDCARH register. The carrier low signal is selected by configuring the MDCL <3:0> bits in the MDCARL register.
22.4
Carrier Synchronization
During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal can be enabled by setting the MDCHSYNC bit in the MDCARH register. Synchronization for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 22-1 through Figure 22-5 show timing diagrams of using various synchronization methods.
22.2
Modulator Signal Sources
The modulator signal can be supplied from the following sources: * * * * * * * CCP1 Signal MSSP1 SDO1 Signal (SPI Mode Only) Comparator C1 Signal Comparator C2 Signal (PIC16F/LF1823 only) EUSART TX Signal External Signal on MDMIN1 pin MDBIT bit in the MDCON register
The modulator signal is selected by configuring the MDMS <3:0> bits in the MDSRC register.
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 22-2:
Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1
ON OFF KEYING (OOK) SYNCHRONIZATION
EXAMPLE 22-1:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State
NO SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 0)
CARH
CARL
CARH
CARL
FIGURE 22-3:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State
CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0)
CARH
both
CARL
CARH
both
CARL
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Preliminary
DS41413A-page 191
PIC12F/LF1822/16F/LF1823
FIGURE 22-4:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State CARH CARL CARH CARL
CARRIER LOW SYNCHRONIZATION (MDSHSYNC = 0, MDCLSYNC = 1)
FIGURE 22-5:
Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State
FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1)
Falling edges used to sync
CARH
CARL
CARH
CARL
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
22.5 CARRIER SOURCE POLARITY SELECT 22.12 Effects of a Reset
Upon any device Reset, the Data Signal Modulator module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values.
The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCARH register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCARL register.
22.6
CARRIER SOURCE PIN DISABLE
Some peripherals assert control over their corresponding output pin when they are enabled. For example, when the CCP1 module is enabled, the output of CCP1 is connected to the CCP1 pin. This default connection to a pin can be disabled by setting the MDCHODIS bit in the MDCARH register for the carrier high source and the MDCLODIS bit in the MDCARL register for the carrier low source.
22.7
PROGRAMMABLE MODULATOR DATA
The MDBIT of the MDCON register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation.
22.8
MODULATOR SOURCE PIN DISABLE
The modulator source default connection to a pin can be disabled by setting the MDMSODIS bit in the MDSRC register.
22.9
MODULATED OUTPUT POLARITY
The modulated output signal provided on the MDOUT pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON register.
22.10 SLEW RATE CONTROL
The slew rate limitation on the output port pin can be disabled. The slew rate limitation can be removed by clearing the MDSLR bit in the MDCON register.
22.11 OPERATION IN SLEEP MODE
The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep.
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Preliminary
DS41413A-page 193
PIC12F/LF1822/16F/LF1823
REGISTER 22-1:
R/W-0/0 MDEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDEN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output MDOE: Modulator Module Pin Output Enable bit 1 = Modulator pin output enabled 0 = Modulator pin output disabled MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting enabled 0 = MDOUT pin slew rate limiting disabled MDOPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted MDOUT: Modulator Output bit Displays the current output value of the Modulator module.(1) Unimplemented: Read as `0' MDBIT: Allows software to manually set modulation source input to module(1) The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. MDBIT must be selected as the modulation source in the MDSRC register for this operation. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCON: MODULATION CONTROL REGISTER
R/W-1/1 MDSLR R/W-0/0 MDOPOL R/W-0/0 MDOUT U-0 -- U-0 -- R/W-0/0 MDBIT bit 0 MDOE
R/W-0/0
bit 6
bit 5
bit 4
bit 3 bit 2-1 bit 0 Note 1: 2:
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Preliminary
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PIC12F/LF1822/16F/LF1823
REGISTER 22-2:
R/W-x/u MDMSODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDMSODIS: Modulation Source Output Disable 1 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDMS<3:0>) is enabled Unimplemented: Read as `0' MDMS<3:0> Modulation Source Selection bits 1111 = Reserved. No channel connected. 1110 = Reserved. No channel connected. 1101 = Reserved. No channel connected. 1100 = Reserved. No channel connected. 1011 = Reserved. No channel connected. 1010 = EUSART TX output 1001 = Reserved. No channel selected. 1000 = MSSP1 SDOx output 0111 = Comparator 2 output (PIC16F/LF1823 only. PIC12F/LF1822; Reserved, no channel connected.) 0110 = Comparator 1 output 0101 = Reserved. No channel connected. 0100 = Reserved. No channel connected. 0011 = Reserved. No channel connected. 0010 = CCP1 output (PWM Output mode only) 0001 = MDMIN port pin 0000 = MDBIT bit of MDCON register is modulation source Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDSRC: MODULATION SOURCE CONTROL REGISTER
U-0 -- U-0 -- U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDMS<3:0>
bit 6-4 bit 3-0
Note 1:
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Preliminary
DS41413A-page 195
PIC12F/LF1822/16F/LF1823
REGISTER 22-3:
R/W-x/u MDCHODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDCHODIS: Modulator High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCH<3:0>) is enabled MDCHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted MDCHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator Output is not synchronized to the high time carrier signal(1) Unimplemented: Read as `0' MDCH<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. * * * 1000 = Reserved. No channel connected. 0111 = Reserved. No channel connected. 0110 = Reserved. No channel connected. 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = Reserved. No channel connected. 0001 = MDCIN1 port pin 0000 = VSS Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER
R/W-x/u MDCHSYNC U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDCH<3:0>
R/W-x/u MDCHPOL
bit 6
bit 5
bit 4 bit 3-0
Note 1:
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
REGISTER 22-4:
R/W-x/u MDCLODIS bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared MDCLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is disabled 0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register) is enabled MDCLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted MDCLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator Output is not synchronized to the low time carrier signal(1) Unimplemented: Read as `0' MDCL<3:0> Modulator Data High Carrier Selection bits (1) 1111 = Reserved. No channel connected. * * * 0101 = Reserved. No channel connected. 0100 = CCP1 output (PWM Output mode only) 0011 = Reference Clock module signal 0010 = Reserved. No channel connected. 0001 = MDCIN1 port pin 0000 = VSS Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
R/W-x/u MDCLSYNC U-0 -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u bit 0 MDCL<3:0>
R/W-x/u MDCLPOL
bit 6
bit 5
bit 4 bit 3-0
Note 1:
TABLE 22-1:
Name MDCARH MDCARL MDCON MDSRC Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE
Bit 7 Bit 6 MDCHPOL MDCLPOL MDOE -- Bit 5 MDCHSYNC MDCLSYNC MDSLR -- Bit 4 -- -- MDOPOL -- MDOUT Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 196 197 MDBIT 194 195
MDCHODIS MDCLODIS MDEN MDMSODIS
MDCH<3:0> MDCL<3:0> -- -- MDMS<3:0>
-- = unimplemented, read as `0'. Shaded cells are not used in the Data Signal Modulator mode.
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Preliminary
DS41413A-page 197
PIC12F/LF1822/16F/LF1823
NOTES:
DS41413A-page 198
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
23.0 CAPTURE/COMPARE/PWM MODULES
The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains one Enhanced Capture/ Compare/PWM module (ECCP1). The Full-Bridge ECCP module has four available I/O pins, while the Half-Bridge ECCP module only has two. See Table 23-1.
TABLE 23-1:
PWM RESOURCES
ECCP1 Enhanced PWM Half-Bridge Enhanced PWM Full-Bridge
Device Name PIC12F/LF1822 PIC16F/LF1823
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Preliminary
DS41413A-page 199
PIC12F/LF1822/16F/LF1823
23.1 Capture Mode
23.1.2 TIMER1 MODE RESOURCE
Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCP1 pin, the 16-bit CCPR1H:CCPR1L register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP1 module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 20.0 "Timer1 Module with Gate Control" for more information on configuring Timer1.
23.1.3
SOFTWARE INTERRUPT MODE
When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPR1H, CCPR1L register pair is read, the old captured value is overwritten by the new captured value. Figure 23-1 shows a simplified diagram of the Capture operation.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP1IE interrupt enable bit of the PIE1 register clear to avoid false interrupts. Additionally, the user should clear the CCP1IF interrupt flag bit of the PIR1 register following any change in Operating mode. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
23.1.1
CCP1 PIN CONFIGURATION 23.1.4
In Capture mode, the CCP1 pin should be configured as an input by setting the associated TRIS control bit. Also, the CCP1 pin function may be moved to alternative pins using the APFCON register. Refer to Section 12.1 "Alternate Pin Function" for more details. Note: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
CCP1 PRESCALER
There are four prescaler settings specified by the CCP1M<3:0> bits of the CCP1CON register. Whenever the CCP1 module is turned off, or the CCP1 module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCP1CON register before changing the prescaler. Example 23-1 demonstrates the code to perform this function.
FIGURE 23-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
Set Flag bit CCP1IF (PIR1 register)
EXAMPLE 23-1:
BANKSEL CCP1CON
Prescaler 1, 4, 16 CCP1 pin
CHANGING BETWEEN CAPTURE PRESCALERS
CCPR1H and Edge Detect Capture Enable TMR1H
CCPR1L
CLRF MOVLW
TMR1L
MOVWF
CCP1M<3:0> System Clock (FOSC)
;Set Bank bits to point ;to CCP1CON CCP1CON ;Turn CCP1 module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP1 ON CCP1CON ;Load CCP1CON with this ;value
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PIC12F/LF1822/16F/LF1823
23.1.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.
TABLE 23-2:
Name CCP1CON CCPR1L CCPR1H INTCON PIE1
PIE2
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 221 200 200 IOCIE SSP1IE
BCL1IE
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
Capture/Compare/PWM Register x Low Byte (LSB) Capture/Compare/PWM Register x High Byte (MSB) GIE TMR1GIE
OSFIE
PEIE ADIE
C2IE(1)
TMR0IE RCIE
C1IE
INTE TXIE
EEIE
TMR0IF CCP1IE
--
INTF TMR2IE
--
IOCIF TMR1IE
--
89
90
91
PIR1
PIR2
TMR1GIF
OSFIF
ADIF
C2IF(1)
RCIF
C1IF
TXIF
EEIF
SSP1IF
BCL1IF
CCP1IF
--
TMR2IF
--
TMR1IF
--
92
93
T1CON T1GCON TMR1L TMR1H TRISA TRISC
(1)
TMR1CS<1:0> TMR1GE T1GPOL
T1CKPS<1:0> T1GTM
T1OSCEN
T1SYNC T1GVAL
--
TMR1ON
180 181 172 172
T1GSPM T1GGO/DONE
T1GSS<1:0>
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- -- -- TRISA5 TRISC5 TRISA4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0
121 125
Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by Capture mode. Note 1: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 201
PIC12F/LF1822/16F/LF1823
23.2 Compare Mode
23.2.2 TIMER1 MODE RESOURCE
Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPR1H:CCPR1L register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: * * * * * Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 20.0 "Timer1 Module with Gate Control" for more information on configuring Timer1. Note: Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCP1 pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.
The action on the pin is based on the value of the CCP1M<3:0> control bits of the CCP1CON register. At the same time, the interrupt flag CCP1IF bit is set. All Compare modes can generate an interrupt. Figure 23-2 shows a simplified diagram of the Compare operation.
23.2.3
SOFTWARE INTERRUPT MODE
FIGURE 23-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1M<3:0> Mode Select Set CCP1IF Interrupt Flag (PIR1) 4 CCPR1H CCPR1L
When Generate Software Interrupt mode is chosen (CCP1M<3:0> = 1010), the CCP1 module does not assert control of the CCP1 pin (see the CCP1CON register).
23.2.4
SPECIAL EVENT TRIGGER
When Special Event Trigger mode is chosen (CCP1M<3:0> = 1011), the CCP1 module does the following: * Resets Timer1 * Starts an ADC conversion if ADC is enabled The CCP1 module does not assert control of the CCP1 pin in this mode. The Special Event Trigger output of the CCP1 occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPR1H, CCPR1L register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Special Event Trigger output starts an A/D conversion (if the A/D module is enabled). This allows the CCPR1H, CCPR1L register pair to effectively provide a 16-bit programmable period register for Timer1. Note 1: The Special Event Trigger from the CCP1 module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring.
CCP1 Pin
Q
S R
Output Logic
Match
Comparator TMR1H TMR1L
TRIS Output Enable Special Event Trigger
Special Event Trigger will:
* CCP1: Reset Timer1, but not set interrupt flag bit TMR1IF and set bit GO/DONE (ADCON0<1>).
23.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by clearing the associated TRIS bit. Also, the CCP1 pin function may be moved to alternative pins using the APFCON register. Refer to Section 12.1 "Alternate Pin Function" for more details. Note: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the PORT I/O data latch.
23.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep.
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PIC12F/LF1822/16F/LF1823
TABLE 23-3:
Name CCP1CON CCPR1L CCPR1H INTCON PIE1 PIE2 PIR1 PIR2 T1CON T1GCON TMR1L TMR1H TRISA TRISC(1)
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 221 200 200 IOCIE SSP1IE BCL1IE SSP1IF BCL1IF T1OSCEN T1GGO/DONE TMR0IF CCP1IE -- CCP1IF -- T1SYNC T1GVAL INTF TMR2IE -- TMR2IF -- -- IOCIF TMR1IE -- TMR1IF -- TMR1ON 89 90 91 92 93 180 181 172 172 TRISA1 TRISC1 TRISA0 TRISC0 121 125
P1M<1:0>
DC1B<1:0>
CCP1M<3:0>
Capture/Compare/PWM Register 1 Low Byte (LSB) Capture/Compare/PWM Register 1 High Byte (MSB) GIE TMR1GIE OSFIE TMR1GIF OSFIF TMR1GE PEIE ADIE C2IE(1) ADIF C2IF(1) T1GPOL TMR0IE RCIE C1IE RCIF C1IF T1GTM INTE TXIE EEIE TXIF EEIF T1GSPM
TMR1CS<1:0>
T1CKPS<1:0>
T1GSS<1:0>
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- -- -- TRISA5 TRISC5 TRISA4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2
Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by Compare mode. Note 1: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 203
PIC12F/LF1822/16F/LF1823
23.3 PWM Overview
FIGURE 23-3:
Period Pulse Width
Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 23-3 shows a typical waveform of the PWM signal.
CCP1 PWM OUTPUT SIGNAL
TMR2 = PR2 TMR2 = CCPR1H:CCP1CON<5:4>
TMR2 = 0
FIGURE 23-4:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H(2) (Slave) CCP1 Comparator
(1)
R S
Q
TMR2
TRIS Comparator
23.3.1
STANDARD PWM OPERATION
PR2
The standard PWM mode generates a Pulse-Width modulation (PWM) signal on the CCP1 pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: * * * * PR2 registers T2CON registers CCPR1L registers CCP1CON registers
Clear Timer, toggle CCP1 pin and latch duty cycle
Note 1:
2:
The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register.
Figure 23-4 shows a simplified block diagram of PWM operation. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin.
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
23.3.2 SETUP FOR PWM OPERATION
The following steps should be taken when configuring the CCP1 module for standard PWM operation: 1. 2. 3. Disable the CCP1 pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP1 module for the PWM mode by loading the CCP1CON register with the appropriate values. Load the CCPR1L register and the DC1B1 bits of the CCP1CON register, with the PWM duty cycle value. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. * Configure the T2CKPS bits of the T2CON register with the Timer prescale value. * Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: * Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note below. * Enable the CCP1 pin output driver by clearing the associated TRIS bit. Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is latched from CCPR1L into CCPR1H. Note: The Timer postscaler (see Section 21.1 "Timer2 Operation") is not used in the determination of the PWM frequency.
4.
23.3.4
PWM DUTY CYCLE
5.
6.
The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPR1L register and DC1B<1:0> bits of the CCP1CON register. The CCPR1L contains the eight MSbs and the DC1B<1:0> bits of the CCP1CON register contain the two LSbs. CCPR1L and DC1B<1:0> bits of the CCP1CON register can be written to at any time. The duty cycle value is not latched into CCPR1H until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPR1H register is read-only. Equation 23-2 is used to calculate the PWM pulse width. Equation 23-3 is used to calculate the PWM duty cycle ratio.
EQUATION 23-2:
PULSE WIDTH
Pulse Width = CCPR1L:CCP1CON<5:4> TOSC (TMR2 Prescale Value)
23.3.3
PWM PERIOD EQUATION 23-3: DUTY CYCLE RATIO
The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 23-1.
EQUATION 23-1:
PWM PERIOD
(TMR2 Prescale Value)
CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ---------------------------------------------------------------------4 PRx + 1 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or 2 bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPR1H and 2-bit latch, then the CCP1 pin is cleared (see Figure 23-4).
PWM Period = PR2 + 1 4 TOSC
Note 1:
TOSC = 1/FOSC
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 205
PIC12F/LF1822/16F/LF1823
23.3.5 PWM RESOLUTION EQUATION 23-4: PWM RESOLUTION
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 23-4. Note: log 4 PR2 + 1 Resolution = ----------------------------------------- bits log 2
If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged.
TABLE 23-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 32 MHz)
1.95 kHz 16 0xFF 10 7.81 kHz 4 0xFF 10 31.25 kHz 1 0xFF 10 125 kHz 1 0x3F 8 250 kHz 1 0x1F 7 333.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 23-5:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 6.6
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 23-6:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
1.22 kHz 16 0x65 8 4.90 kHz 4 0x65 8 19.61 kHz 1 0x65 8 76.92 kHz 1 0x19 6 153.85 kHz 1 0x0C 5 200.0 kHz 1 0x09 5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
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Preliminary
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PIC12F/LF1822/16F/LF1823
23.3.6 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state.
23.3.7
CHANGES IN SYSTEM CLOCK FREQUENCY
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 5.0 "Oscillator Module (With Fail-Safe Clock Monitor)" for additional details.
23.3.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
TABLE 23-7:
Name CCP1CON INTCON PIE1 PIR1 PR2 T2CON TMR2 TRISA TRISC(1)
SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 221 IOCIF TMR1IE TMR1IF 89 90 92 184* T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 186 184 TRISA5 TRISC5 TRISA4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0 121 125
P1M<1:0> GIE TMR1GIE TMR1GIF -- Timer2 Module Register -- -- -- -- PEIE ADIE ADIF
DC1B<1:0> TMR0IE RCIE RCIF INTE TXIE TXIF IOCIE SSP1IE SSP1IF
CCP1M<3:0> TMR0IF CCP1IE CCP1IF INTF TMR2IE TMR2IF
Timer2 Period Register
Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 207
PIC12F/LF1822/16F/LF1823
23.4 PWM (Enhanced Mode)
The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: * * * * PR2 registers T2CON registers CCPR1L registers CCP1CON registers The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the bits CCP1M<3:0> in the CCP1CON register appropriately. Figure 23-5 shows an example of a simplified block diagram of the Enhanced PWM module. Table 23-8 shows the pin assignments for various Enhanced PWM modes. Note 1: The corresponding TRIS bit must be cleared to enable the PWM output on the CCP1 pin. 2: Clearing the CCP1CON register will relinquish control of the CCP1 pin. 3: Any pin not used in the enhanced PWM mode is available for alternate pin functions, if applicable. 4: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal.
The ECCP modules have the following additional PWM registers which control Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering modes: * CCP1AS registers * PSTR1CON registers * PWM1CON registers The enhanced PWM module can generate the following four PWM Output modes: * * * * Single PWM Half-Bridge PWM Full-Bridge PWM (PIC16F/LF1823 only) Single PWM with PWM Steering Mode
To select an Enhanced PWM Output mode, the P1M bits of the CCP1CON register must be configured appropriately.
FIGURE 23-5:
Duty Cycle Registers CCPR1L
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
DC1B<1:0> P1M<1:0> 2 CCP1M<3:0> 4
CCP1/P1A TRISx CCPR1H (Slave) Comparator R Q P1B Output Controller P1C(2) TMR2 (1) S P1D(2) Clear Timer, toggle PWM pin and latch duty cycle PWM1CON TRISx TRISx TRISx
CCP1/P1A
P1B
P1C(2)
Comparator
P1D(2)
PR2
Note
1: 2:
The 8-bit timer TMR1 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base. PIC16F/LF1823 only.
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 23-8:
ECCP Mode Single Half-Bridge Full-Bridge, Forward Note 1: 2:
(2)
EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
P1M<1:0> 00 10 01 11 CCP1/P1A Yes(1) Yes Yes Yes P1B Yes(1) Yes Yes Yes P1C(2) Yes(1) No Yes Yes P1D(2) Yes(1) No Yes Yes
Full-Bridge, Reverse(2)
PWM Steering enables outputs in Single mode. PIC16F/LF1823 only.
FIGURE 23-6:
PxM<1:0>
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE)
Signal 0 Pulse Width Period PRX+1
00
(Single Output)
PxA Modulated Delay PxA Modulated Delay
10
(Half-Bridge)
PxB Modulated PxA Active
01
(Full-Bridge, Forward)
PxB Inactive PxC Inactive PxD Modulated PxA Inactive
11
(Full-Bridge, Reverse)
PxB Modulated PxC Active PxD Inactive
Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>)
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Preliminary
DS41413A-page 209
PIC12F/LF1822/16F/LF1823
FIGURE 23-7:
PxM<1:0>
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
Signal 0 Pulse Width Period PRx+1
00
(Single Output)
PxA Modulated PxA Modulated
10
(Half-Bridge)
Delay PxB Modulated PxA Active
Delay
01
(Full-Bridge, Forward)
PxB Inactive PxC Inactive PxD Modulated PxA Inactive
11
(Full-Bridge, Reverse)
PxB Modulated PxC Active PxD Inactive
Relationships: * Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) * Pulse Width = TOSC * (CCPRxL<7:0>:CCPxCON<5:4>) * (TMRx Prescale Value) * Delay = 4 * TOSC * (PWMxCON<6:0>)
DS41413A-page 210
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
23.4.1 HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 23-9). This mode can be used for Half-Bridge applications, as shown in Figure 23-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in HalfBridge power devices. The value of the PDC<6:0> bits of the PWM1CON register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. See Section 23.4.5 "Programmable Dead-Band Delay Mode" for more details of the dead-band delay operations. Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs.
FIGURE 23-8:
Period
EXAMPLE OF HALFBRIDGE PWM OUTPUT
Period
Pulse Width P1A(2) td P1B(2)
(1)
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high.
FIGURE 23-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A
+ Load + -
FET Driver P1B
Half-Bridge Output Driving a Full-Bridge Circuit V+
FET Driver P1A Load
FET Driver
FET Driver P1B
FET Driver
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Preliminary
DS41413A-page 211
PIC12F/LF1822/16F/LF1823
23.4.2 FULL-BRIDGE MODE (PIC16F/LF1823 ONLY)
In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 23-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 23-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 23-11. P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs.
FIGURE 23-10:
EXAMPLE OF FULL-BRIDGE APPLICATION
V+
FET Driver P1A
QA
QC
FET Driver
P1B FET Driver
Load FET Driver
P1C
QB
QD
VP1D
DS41413A-page 212
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 23-11:
Forward Mode Period P1A
(2)
EXAMPLE OF FULL-BRIDGE PWM OUTPUT
Pulse Width P1B(2)
P1C(2)
P1D(2)
(1) (1)
Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2)
P1D(2)
(1) (1)
Note 1: 2:
At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high.
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Preliminary
DS41413A-page 213
PIC12F/LF1822/16F/LF1823
23.4.2.1 Direction Change in Full-Bridge Mode
In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register. The following sequence occurs four Timer cycles prior to the end of the current PWM period: * The modulated outputs (P1B and P1D) are placed in their inactive state. * The associated unmodulated outputs (P1A and P1C) are switched to drive in the opposite direction. * PWM modulation resumes at the beginning of the next period. See Figure 23-12 for an illustration of this sequence. The Full-Bridge mode does not provide dead-band delay. As one output is modulated at a time, dead-band delay is generally not required. There is a situation where dead-band delay is required. This situation occurs when both of the following conditions are true: 1. 2. The direction of the PWM output changes when the duty cycle of the output is at or near 100%. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time.
Figure 23-13 shows an example of the PWM direction changing from forward to reverse, at a near 100% duty cycle. In this example, at time t1, the output P1A and P1D become inactive, while output P1C becomes active. Since the turn off time of the power devices is longer than the turn on time, a shoot-through current will flow through power devices QC and QD (see Figure 23-10) for the duration of `t'. The same phenomenon will occur to power devices QA and QB for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce PWM duty cycle for one PWM period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on.
Other options to prevent shoot-through current may exist.
FIGURE 23-12:
Signal
EXAMPLE OF PWM DIRECTION CHANGE
Period(1) Period
P1A (Active-High) P1B (Active-High) P1C (Active-High) P1D (Active-High) Pulse Width Note 1: 2: The direction bit P1M1 of the CCP1CON register is written any time during the PWM cycle. When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time. The length of this time is four Timer counts.
(2)
Pulse Width
DS41413A-page 214
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 23-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period t1 Reverse Period
P1A P1B P1C P1D PW
PW TON
External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF - TON
Note 1: 2: 3:
All signals are shown as active-high. TON is the turn-on delay of power switch QC and its driver. TOFF is the turn-off delay of power switch QD and its driver.
23.4.3
ENHANCED PWM AUTOSHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCP1AS<2:0> bits of the CCP1AS register. A shutdown event may be generated by: * A logic `0' on the INT pin * Comparator C1 * Setting the CCP1ASE bit in firmware A shutdown condition is indicated by the CCP1ASE (Auto-Shutdown Event Status) bit of the CCP1AS register. If the bit is a `0', the PWM pins are operating normally. If the bit is a `1', the PWM outputs are in the shutdown state. When a shutdown event occurs, two things happen: The CCP1ASE bit is set to `1'. The CCP1ASE will remain set until cleared in firmware or an auto-restart occurs (see Section 23.4.4 "Auto-Restart Mode"). The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [P1A/P1C] and [P1B/P1D]. The state
of each pin pair is determined by the PSS1AC and PSS1BD bits of the CCP1AS register. Each pin pair may be placed into one of three states: * Drive logic `1' * Drive logic `0' * Tri-state (high-impedance) Note 1: The auto-shutdown condition is a levelbased signal, not an edge-based signal. As long as the level is present, the autoshutdown will persist. 2: Writing to the CCP1ASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.
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Preliminary
DS41413A-page 215
PIC12F/LF1822/16F/LF1823
FIGURE 23-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (P1RSEN = 0)
Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCP1ASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCP1ASE Cleared by Firmware Timer Overflow Missing Pulse (CCP1ASE not clear) Timer Overflow Timer Overflow
23.4.4
AUTO-RESTART MODE
The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the P1RSEN bit in the PWM1CON register.
If auto-restart is enabled, the CCP1ASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the CCP1ASE bit will be cleared via hardware and normal operation will resume.
FIGURE 23-15:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART (P1RSEN = 1)
Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow PWM Period Timer Overflow Missing Pulse (CCP1ASE not clear) Timer Overflow Timer Overflow
PWM Activity Start of PWM Period Shutdown Event CCP1ASE bit Shutdown Event Occurs Shutdown Event Clears PWM Resumes CCP1ASE Cleared by Hardware
DS41413A-page 216
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
23.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 23-16:
Period Pulse Width P1A(2) td P1B(2)
(1)
EXAMPLE OF HALFBRIDGE PWM OUTPUT
Period
In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off. During this brief interval, a very high current (shootthrough current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable deadband delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. See Figure 23-16 for illustration. The lower seven bits of the associated PWM1CON register (Register 23-3) sets the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC).
td
(1)
(1)
td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high.
FIGURE 23-17:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit ("Push-Pull") FET Driver P1A
+ V Load + V -
FET Driver P1B
V-
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Preliminary
DS41413A-page 217
PIC12F/LF1822/16F/LF1823
23.4.6 PWM STEERING MODE FIGURE 23-18:
STR1A P1A Signal CCP1M1 PORT Data STR1B CCP1M0 PORT Data 1 0 P1A pin
In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR1 bits of the PSTR1CON register, as shown in Table 23-8. Note: The associated TRIS bits must be set to output (`0') to enable the pin output driver in order to see the PWM signal on the pin.
SIMPLIFIED STEERING BLOCK DIAGRAM
1 0 TRIS
P1B pin
STR1C CCP1M1 PORT Data STR1D CCP1M0 PORT Data 1 0 1 0
TRIS P1C pin(3)
While the PWM Steering mode is active, the CCP1M<1:0> bits of the CCP1CON register determine the polarity of the output pins. The PWM auto-shutdown operation also applies to PWM Steering mode as described in Section 23.4.3 "Enhanced PWM Auto-shutdown mode". An autoshutdown event will only affect pins that have PWM outputs enabled.
TRIS P1D pin(3)
TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> = 00 and CCP1M<3:2> = 11. Single PWM output requires setting at least one of the STR1 bits. PIC16F/LF1823 only.
2: 3:
DS41413A-page 218
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
23.4.6.1 Steering Synchronization
The STR1SYNC bit of the PSTR1CON register gives the user two selections of when the steering event will happen. When the STR1SYNC bit is `0', the steering event will happen at the end of the instruction that writes to the PSTR1CON register. In this case, the output signal at the output pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STR1SYNC bit is `1', the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figures 23-19 and 23-20 illustrate the timing diagrams of the PWM steering depending on the STR1SYNC setting. drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enable is not recommended since it may result in damage to the application circuits. The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the highimpedance state. The external circuits must keep the power switch devices in the Off state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s).
23.4.7
START-UP CONSIDERATIONS
When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCP1M<1:0> bits of the CCP1CON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (P1A/P1C and P1B/P1D). The PWM output polarities must be selected before the PWM pin output
FIGURE 23-19:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STR1SYNC = 0)
PWM Period
PWM STR1
P1
PORT Data P1n = PWM
PORT Data
FIGURE 23-20:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STR1SYNC = 1)
PWM
STR1
P1
PORT Data P1n = PWM
PORT Data
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TABLE 23-9:
Name CCP1CON CCP1AS INTCON PIE1 PIR1 PR2 PSTR1CON PWM1CON T2CON TMR2 TRISA TRISC
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH ENHANCED PWM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page 221 222 89 90 92 184* -- STR1SYNC STR1D(1) P1DC<6:0> T2OUTPS<3:0> TMR2ON T2CKPS<:0>1 STR1C(1) STR1B STR1A 224 223 186 184 TRISA5 TRISC5 TRISA4 TRISC4 TRISA3 TRISC3 TRISA2 TRISC2 TRISA1 TRISC1 TRISA0 TRISC0 121 125 IOCIF TMR1IE TMR1IF
P1M<1:0> CCP1ASE GIE TMR1GIE TMR1GIF -- P1RSEN -- Timer2 Module Register -- -- -- -- PEIE ADIE ADIF --
DC1B<1:0> CCP1AS<2:0> TMR0IE RCIE RCIF INTE TXIE TXIF IOCIE SSP1IE SSP1IF
CCP1M<3:0> PSS1AC<1:0> TMR0IF CCP1IE CCP1IF PSS1BD<1:0> INTF TMR2IE TMR2IF
Timer2 Period Register
Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the PWM. * Page provides register information. Note 1: PIC16F/LF1823 only.
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REGISTER 23-1:
R/W-00 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-6 W = Writable bit x = Bit is unknown `0' = Bit is cleared P1M<1:0>: Enhanced PWM Output Configuration bits(1) Capture mode: Unused Compare mode: Unused PWM mode: If CCP1M<3:2> = 00, 01, 10: xx = P1A assigned as Capture/Compare input; P1B, P1C, P1D assigned as port pins(1) If CCP1M<3:2> = 11: 00 = Single output; P1A modulated; P1B, P1C, P1D assigned as port pins 01 = Full-Bridge output forward; P1D modulated; P1A active; P1B, P1C inactive(1) 10 = Half-Bridge output; P1A, P1B modulated with dead-band control; P1C, P1D assigned as port pins 11 = Full-Bridge output reverse; P1B modulated; P1C active; P1A, P1D inactive(1) bit 5-4 DC1B<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L. bit 3-0 CCP1M<3:0>: ECCP1 Mode Select bits 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = Capture/Compare/PWM off (resets ECCP1 module) Reserved Compare mode: toggle output on match Reserved Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge Compare mode: initialize ECCP1 pin low; set output on compare match (set CCP1IF) Compare mode: initialize ECCP1 pin high; clear output on compare match (set CCP1IF) Compare mode: generate software interrupt only; ECCP1 pin reverts to I/O state Compare mode: Special Event Trigger (CCP1 resets TMR1, sets CCP1IF bit, and starts A/D conversion if A/D module is enabled) U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Reset P1M<1:0>(1)
CCP1CON: CCP1 CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 DC1B<1:0> CCP1M<3:0>
R/W-0/0
PWM mode: 1100 = PWM mode: P1A, P1C active-high; P1B, P1D active-high 1101 = PWM mode: P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode: P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode: P1A, P1C active-low; P1B, P1D active-low Note 1: PIC16F/LF1823 only.
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PIC12F/LF1822/16F/LF1823
REGISTER 23-2:
R/W-0/0 CCP1ASE bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CCP1ASE: CCP1 Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; CCP1 outputs are in shutdown state 0 = CCP1 outputs are operating CC1PAS<2:0>: CCP1 Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator C1 output low(1) 010 = Comparator C2 output low(1, 2) 011 = Either Comparator C1 or C2 low(1, 2) 100 = VIL on INT pin 101 = VIL on INT pin or Comparator C1 low(1) 110 = VIL on INT pin or Comparator C2 low(1, 2) 111 = VIL on INT pin or Comparator C1 or Comparator C2 low(1, 2) PSS1AC<1:0>: Pins P1A and P1C Shutdown State Control bits(2) 00 = Drive pins P1A and P1C to `0' (2) 01 = Drive pins P1A and P1C to `1' (2) 1x = Pins P1A and P1C tri-state(2) PSS1BD<1:0>: Pins P1B and P1D Shutdown State Control bits(2) 00 = Drive pins P1B and P1D to `0' 01 = Drive pins P1B and P1D to `1' 1x = Pins P1B and P1D tri-state If C1SYNC is enabled, the shutdown will be delayed by Timer1. C2, P1C and P1D available on PIC16F/LF1823 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CCP1AS: CCP1 AUTO-SHUTDOWN CONTROL REGISTER
R/W-0/0 CCP1AS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 PSS1AC<1:0> PSS1BD<1:0>
R/W-0/0
bit 6-4
bit 3-2
bit 1-0
Note 1: 2:
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PIC12F/LF1822/16F/LF1823
REGISTER 23-3:
R/W-0/0 P1RSEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared P1RSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCP1ASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, CCP1ASE must be cleared in software to restart the PWM P1DC<6:0>: PWM Delay Count bits P1DC1 = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it transitions active Bit resets to `0' with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 P1DC<6:0> bit 0 R/W-0/0 R/W-0/0 R/W-0/0
R/W-0/0
bit 6-0
Note 1:
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REGISTER 23-4:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-5 bit 4 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' STR1SYNC: Steering Sync bit 1 = Output steering update occurs on next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary STR1D: Steering Enable bit D(2) 1 = P1D pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1D pin is assigned to port pin STR1C: Steering Enable bit C(2) 1 = P1C pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1C pin is assigned to port pin STR1B: Steering Enable bit B 1 = P1B pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1B pin is assigned to port pin STR1A: Steering Enable bit A 1 = P1A pin has the PWM waveform with polarity control from CCP1M<1:0> 0 = P1A pin is assigned to port pin The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> = 11 and P1M<1:0> = 00. PIC16F/LF1823 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
PSTR1CON: PWM STEERING CONTROL REGISTER(1)
U-0 -- U-0 -- R/W-0/0 STR1SYNC R/W-0/0 STR1D R/W-0/0 STR1C R/W-0/0 STR1B R/W-1/1 STR1A bit 0
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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PIC12F/LF1822/16F/LF1823
24.0
24.1
MASTER SYNCHRONOUS SERIAL PORT MODULE
Master SSP (MSSP1) Module Overview
The Master Synchronous Serial Port (MSSP1) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP1 module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2CTM) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy chain connection of slave devices
Figure 24-1 is a block diagram of the SPI interface module.
FIGURE 24-1:
MSSP1 BLOCK DIAGRAM (SPI MODE)
Data Bus Read SSP1BUF Reg Write
SDI SSP1SR Reg SDO bit 0 Shift Clock
SS
SS Control Enable Edge Select SSP1M<3:0> 4
2 (CKP, CKE) Clock Select
SCK Edge Select
( TMR22Output )
Prescaler TOSC 4, 16, 64
Baud rate generator (SSP1ADD)
TRIS bit
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Preliminary
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PIC12F/LF1822/16F/LF1823
The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times
Figure 24-2 is a block diagram of the I2C interface module in Master mode. Figure 24-3 is a diagram of the I2C interface module in Slave mode.
FIGURE 24-2:
MSSP1 BLOCK DIAGRAM (I2CTM MASTER MODE)
Internal data bus Read SSP1BUF Write Baud rate generator (SSP1ADD) Shift Clock SSP1SR Clock Cntl MSb Receive Enable (RCEN) LSb Clock arbitrate/BCOL detect (Hold off clock source)
[SSP1M 3:0]
SDA SDA in
Start bit, Stop bit, Acknowledge Generate (SSP1CON2)
SCL
SCL in Bus Collision
Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect
Set/Reset: S, P, SSP1STAT, WCOL, SSP1OV Reset SEN, PEN (SSP1CON2) Set SSP1IF, BCL1IF
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FIGURE 24-3: MSSP1 BLOCK DIAGRAM (I2CTM SLAVE MODE)
Internal Data Bus Read SSP1BUF Reg Shift Clock SSP1SR Reg SDA MSb LSb Write
SCL
SSP1MSK Reg Match Detect SSP1ADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSP1STAT Reg) Addr Match
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Preliminary
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PIC12F/LF1822/16F/LF1823
24.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select. The SPI bus specifies four signal connections: * * * * Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After 8 bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.
Figure 24-1 shows the block diagram of the MSSP1 module when operating in SPI Mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 24-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure 24-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master's SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and
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PIC12F/LF1822/16F/LF1823
FIGURE 24-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK SDO SDI General I/O General I/O General I/O SCK SDI SDO SS SCK SDI SDO SS SCK SDI SDO SS SPI Slave #3 SPI Slave #2 SPI Slave #1
SPI Master
24.2.1
SPI MODE REGISTERS
The MSSP1 module has five registers for SPI mode operation. These are: * * * * * * MSSP1 STATUS register (SSP1STAT) MSSP1 Control Register 1 (SSP1CON1) MSSP1 Control Register 3 (SSP1CON3) MSSP1 Data Buffer register (SSP1BUF) MSSP1 Address register (SSP1ADD) MSSP1 Shift register (SSP1SR) (Not directly accessible)
SSP1CON1 and SSP1STAT are the control and STATUS registers in SPI mode operation. The SSP1CON1 register is readable and writable. The lower 6 bits of the SSP1STAT are read-only. The upper two bits of the SSP1STAT are read/write. In one SPI master mode, SSP1ADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 24.7 "Baud Rate Generator". SSP1SR is the shift register used for shifting data in and out. SSP1BUF provides indirect access to the SSP1SR register. SSP1BUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSP1SR and SSP1BUF together create a buffered receiver. When SSP1SR receives a complete byte, it is transferred to SSP1BUF and the SSP1IF interrupt is set. During transmission, the SSP1BUF is not buffered. A write to SSP1BUF will write to both SSP1BUF and SSP1SR.
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Preliminary
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PIC12F/LF1822/16F/LF1823
24.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSP1CON1<5:0> and SSP1STAT<7:6>). These control bits allow the following to be specified: Master mode (SCK1 is the clock output) Slave mode (SCK1 is the clock input) Clock Polarity (Idle state of SCK1) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK1) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSP1 Enable bit, SSP1EN of the SSP1CON1 register must be set. To reset or reconfigure SPI mode, clear the SSP1EN bit, re-initialize the SSP1CONx registers and then set the SSP1EN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI must have corresponding TRIS bit set * SDO must have corresponding TRIS bit cleared * SCK (Master mode) must have corresponding TRIS bit cleared * SCK (Slave mode) must have corresponding TRIS bit set * SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP1 consists of a transmit/receive shift register (SSP1SR) and a buffer register (SSP1BUF). The SSP1SR shifts the data in and out of the device, MSb first. The SSP1BUF holds the data that was written to the SSP1SR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSP1BUF register. Then, the Buffer Full Detect bit, BF of the SSP1STAT register, and the interrupt flag bit, SSP1IF, are set. This double-buffering of the received data (SSP1BUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSP1BUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL, of the SSP1CON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSP1BUF register to complete successfully. * * * * When the application software is expecting to receive valid data, the SSP1BUF should be read before the next byte of data to transfer is written to the SSP1BUF. The Buffer Full bit, BF of the SSP1STAT register, indicates when SSP1BUF has been loaded with the received data (transmission is complete). When the SSP1BUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP1 interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSP1SR is not directly readable or writable and can only be accessed by addressing the SSP1BUF register. Additionally, the SSP1STAT register indicates the various Status conditions.
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PIC12F/LF1822/16F/LF1823
FIGURE 24-5: SPI MASTER/SLAVE CONNECTION
SPI Slave SSP1M<3:0> = 010x SDO SDI Serial Input Buffer (SSP1BUF)
SPI Master SSP1M<3:0> = 00xx = 1010
Serial Input Buffer (BUF)
Shift Register (SSP1SR) MSb LSb
SDI
SDO MSb SCK SS
Shift Register (SSP1SR) LSb
SCK General I/O Processor 1
Serial Clock Slave Select (optional)
Processor 2
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Preliminary
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24.2.3 SPI MASTER MODE
The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 24-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSP1BUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSP1SR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSP1BUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSP1CON1 register and the CKE bit of the SSP1STAT register. This then, would give waveforms for SPI communication as shown in Figure 24-6, Figure 24-8 and Figure 24-9, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 Fosc/(4 * (SSP1ADD + 1))
Figure 24-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSP1BUF is loaded with the received data is shown.
FIGURE 24-6:
Write to SSP1BUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSP1IF SSP1SR to SSP1BUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit 7 bit 7
bit 6 bit 6
bit 5 bit 5
bit 4 bit 4
bit 3 bit 3
bit 2 bit 2
bit 1 bit 1
bit 0 bit 0
bit 7
bit 0
bit 7
bit 0
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24.2.4 SPI SLAVE MODE
24.2.5
In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSP1IF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSP1CON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 24.2.4.1 Daisy-Chain Configuration
SLAVE SELECT SYNCHRONIZATION
The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSP1CON1<3:0> = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSP1CON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSP1STAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSP1EN bit.
The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 24-7 shows the block diagram of a typical daisy-chain connection when operating in SPI Mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSP1CON3 register will enable writes to the SSP1BUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it.
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PIC12F/LF1822/16F/LF1823
FIGURE 24-7: SPI DAISY-CHAIN CONNECTION
SCK SDO SDI General I/O SCK SDI SDO SS SCK SDI SDO SS SCK SDI SDO SS SPI Slave #3 SPI Slave #2 SPI Slave #1
SPI Master
FIGURE 24-8:
SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF SSP1BUF to SSP1SR
SLAVE SELECT SYNCHRONOUS WAVEFORM
Shift register SSP1SR and bit count are reset
SDO
bit 7
bit 6
bit 7
bit 6
bit 0
SDI bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF bit 7
bit 0
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FIGURE 24-9:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSP1BUF Valid SDO SDI bit 7 Input Sample SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 24-10:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSP1BUF Valid SDO SDI
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7 Input Sample
bit 0
SSP1IF Interrupt Flag SSP1SR to SSP1BUF Write Collision detection active
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Preliminary
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24.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP1 interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP1 interrupt flag bit will be set and if enabled, will wake the device.
TABLE 24-1:
Name ANSELA ANSELC APFCON INTCON PIE1 PIR1 SSP1BUF SSP1CON1 SSP1CON3 SSP1STAT TRISA TRISC Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 -- -- Bit 6 -- -- SDOSEL PEIE ADIE ADIF SSPOV PCIE CKE -- -- Bit 5 -- -- SSSEL TMR0IE RCIE RCIF SSPEN SCIE D/A TRISA5 TRISC5 Bit 4 ANSA4 -- -- INTE TXIE TXIF CKP BOEN P TRISA4 TRISC4 SDAHT S TRISA3 TRISC3 Bit 3 -- ANSC3 T1GSEL IOCIE SSP1IE SSP1IF Bit 2 ANSA2 ANSC2 TXCKSEL TMR0IF CCP1IE CCP1IF Bit 1 ANSA1 ANSC1 P1BSEL INTF TMR2IE TMR2IF Bit 0 ANSA0 ANSC0 CCP1SEL IOCIF TMR1IE TMR1IF Register on Page 122 126 118 89 90 92 229* SSPM<3:0> SBCDE R/W TRISA2 TRISC2 AHEN UA TRISA1 TRISC1 DHEN BF TRISA0 TRISC0 275 277 274 121 125
RXDTSEL GIE TMR1GIE TMR1GIF WCOL ACKTIM SMP -- --
Synchronous Serial Port Receive Buffer/Transmit Register
-- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP1 in SPI mode. Page provides register information. PIC16F/LF1823 only.
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.3
I2C MODE OVERVIEW FIGURE 24-11:
The Inter-Integrated Circuit Bus (IC) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A Slave device is controlled through addressing. The I2C bus specifies two signal connections: * Serial Clock (SCL) * Serial Data (SDA) Figure 24-11 shows the block diagram of the MSSP1 module when operating in I2C Mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 24-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. Master SDA
I2C MASTER/ SLAVE CONNECTION
VDD
SCL VDD
SCL Slave SDA
The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 237
PIC12F/LF1822/16F/LF1823
When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
24.3.1
CLOCK STRETCHING
When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.
24.4
I2C Mode Operation
All MSSP1 I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 24.4.1 BYTE FORMAT
24.3.2
ARBITRATION
Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don't match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message.
All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 24.4.2 DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Phillips I2CTM specification. 24.4.3 SDA AND SCL PINS
Selection of any I2C mode with the SSP1EN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 24.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT bit of the SSP1CON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance.
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 24-2:
TERM Transmitter
I2C BUS TERMS
Description
24.4.5
2
START CONDITION
The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave device that has received a Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSP1ADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state.
The I C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 24-10 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 24.4.6 STOP CONDITION
A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected.
24.4.7
RESTART CONDITION
A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address match fails. 24.4.8 START/STOP CONDITION INTERRUPT MASKING
The SCIE and PCIE bits of the SSP1CON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 239
PIC12F/LF1822/16F/LF1823
FIGURE 24-12: I2C START AND STOP CONDITIONS
SDA
SCL S Change of Start Condition Data Allowed Change of Data Allowed Stop Condition P
FIGURE 24-13:
I2C RESTART CONDITION
Sr Change of Data Allowed Restart Condition Change of Data Allowed
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Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.4.9 ACKNOWLEDGE SEQUENCE
24.5
I2C SLAVE MODE OPERATION
The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSP1CON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSP1CON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSP1CON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSP1STAT register or the SSP1OV bit of the SSP1CON1 register are set when a byte is received. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit of the SSP1CON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled.
The MSSP1 Slave mode operates in one of four modes selected in the SSP1M bits of SSP1CON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operated the same as the other modes with SSP1IF additionally getting set upon detection of a Start, Restart, or Stop condition. 24.5.1 SLAVE MODE ADDRESSES
The SSP1ADD register (Register 24-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSP1BUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 24-5) affects the address matching process. See Section 24.5.9 "SSP1 Mask Register" for more information. 24.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 24.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb's of the 10-bit address and stored in bits 2 and 1 of the SSP1ADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSP1ADD with the low address. The low address byte is clocked in and all 8 bits are compared to the low address value in SSP1ADD. Even if there is not an address match; SSP1IF and UA are set, and SCL is held low until SSP1ADD is updated to receive a high byte again. When SSP1ADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 241
PIC12F/LF1822/16F/LF1823
24.5.2 SLAVE RECEPTION 24.5.2.2 7-bit Reception with AHEN and DHEN When the R/W bit of a matching received address byte is clear, the R/W bit of the SSP1STAT register is cleared. The received address is loaded into the SSP1BUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSP1STAT register is set, or bit SSP1OV of the SSP1CON1 register is set. The BOEN bit of the SSP1CON3 register modifies this operation. For more information see Register 24-4. An MSSP1 interrupt is generated for each transferred data byte. Flag bit, SSP1IF, must be cleared by software. When the SEN bit of the SSP1CON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSP1CON1 register, except sometimes in 10-bit mode. See Section 24.2.3 "SPI Master Mode" for more detail. 24.5.2.1 7-bit Addressing Reception Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communcation. Figure 24-15 displays a module using both address and data holding. Figure 24-16 includes the operation with the SEN bit of the SSP1CON2 register set. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSP1IF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSP1IF. 4. Slave can look at the ACKTIM bit of the SSP1CON3 register to determine if the SSP1IF was after or before the ACK. 5. Slave reads the address value from SSP1BUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSP1IF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSP1IF. Note: SSP1IF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to Master is SSP1IF not set 11. SSP1IF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSP1CON3 to determine the source of the interrupt. 13. Slave reads the received data from SSP1BUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. 1.
This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 7-bit Addressing mode. All decisions made by hardware or software and their effect on reception. Figure 24-13 and Figure 24-14 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSP1STAT is set; SSP1IF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSP1IF bit. Software clears SSP1IF. Software reads the received byte from SSP1BUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit of SSP1STAT, and the bus goes idle.
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Preliminary
2010 Microchip Technology Inc.
FIGURE 24-14:
Bus Master sends Stop condition From Slave to Master Receiving Address A5 ACK A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 Receiving Data Receiving Data D1 D0 ACK = 1
2010 Microchip Technology Inc.
3 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared by software Cleared by software SSP1IF set on 9th falling edge of SCL SSP1BUF is read First byte of data is available in SSP1BUF SSP1OV set because SSP1BUF is still full. ACK is not sent.
SDA
A7
A6
SCL
S
1
2
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
PIC12F/LF1822/16F/LF1823
Preliminary
SSP1IF
BF
SSP1OV
DS41413A-page 243
FIGURE 24-15:
DS41413A-page 244
Bus Master sends Stop condition Receive Data A2 A1 R/W=0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 Receive Data D0 ACK A4 A3 4 1 Clock is held low until CKP is set to `1' 2 3 4 5 6 7 8 9 5 6 7 8 9 SEN 1 2 3 4 SEN 5 6 7 8 9 P Cleared by software Cleared by software
falling edge of SCL
Receive Address
SDA
A7
A6
A5
SCL
S
1
2
3
SSP1IF SSP1IF set on 9th
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Preliminary
SSP1BUF is read CKP is written to `1' in software, releasing SCL
BF
First byte of data is available in SSP1BUF
SSP1OV SSP1OV set because SSP1BUF is still full. ACK is not sent.
CKP
2010 Microchip Technology Inc.
CKP is written to `1' in software, releasing SCL
SCL is not held low because ACK= 1
FIGURE 24-16:
Master sends Stop condition
Master Releases SDA to slave for ACK sequence Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data ACK= 1
SDA
Receiving Address
A7 A6 A5 A4 A3 A2 A1
ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 3 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 4 5 6 7 8 9 9 P
2010 Microchip Technology Inc.
If AHEN = 1: SSP1IF is set SSP1IF is set on 9th falling edge of SCL, after ACK Data is read from SSP1BUF Cleared by software No interrupt after not ACK from Slave Address is read from SSBUF Slave software clears ACKDT to ACK the received byte Slave software sets ACKDT to not ACK When DHEN = 1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL
S
1
2
SSP1IF
BF
ACKDT
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
PIC12F/LF1822/16F/LF1823
Preliminary
CKP
When AHEN = 1: CKP is cleared by hardware and SCL is stretched
ACKTIM
ACKTIM set by hardware on 8th falling edge of SCL
S
P
DS41413A-page 245
FIGURE 24-17:
DS41413A-page 246
Master sends Stop condition Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 Receive Data ACK R/W = 0 ACK Master releases SDA to slave for ACK sequence
SDA
Receiving Address
A7 A6 A5 A4 A3 A2 A1
SCL
S
1 5 67 8 1 23 4 5 67 8 9
23 9 34 5 67 8
4
1
2
9
P
SSP1IF Cleared by software No interrupt after if not ACK from Slave SSP1BUF can be read any time before next byte is loaded
BF Received data is available on SSP1BUF
Received address is loaded into SSP1BUF
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
Preliminary
When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM is cleared by hardware on 9th rising edge of SCL
ACKDT
Slave software clears ACKDT to ACK the received byte
Slave sends not ACK CKP is not cleared if not ACK Set by software, release SCL
CKP
When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware on 8th falling edge of SCL
S
2010 Microchip Technology Inc.
P
PIC12F/LF1822/16F/LF1823
24.5.3 SLAVE TRANSMISSION 24.5.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSP1STAT register is set. The received address is loaded into the SSP1BUF register, and an ACK pulse is sent by the slave on the ninth bit. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 24.5.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSP1BUF register which also loads the SSP1SR register. Then the SCL pin should be released by setting the CKP bit of the SSP1CON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSP1CON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSP1BUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP1 interrupt is generated for each data transfer byte. The SSP1IF bit must be cleared by software and the SSP1STAT register is used to determine the status of the byte. The SSP1IF bit is set on the falling edge of the ninth clock pulse. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 24-17 can be used as a reference to this list. Master sends a Start condition on SDA and SCL. 2. S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSP1IF bit. 4. Slave hardware generates an ACK and sets SSP1IF. 5. SSP1IF bit is cleared by user. 6. Software reads the received address from SSP1BUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSP1BUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSP1IF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSP1IF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSP1IF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. 1.
24.5.3.1
Slave Mode Bus Collision
A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSP1CON3 register is set, the BCL1IF bit of the PIRx register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software can use the BCL1IF bit to handle a slave bus collision.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 247
FIGURE 24-18:
Master sends Stop condition Receiving Address D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Transmitting Data Automatic Transmitting Data ACK
DS41413A-page 248
2 3 4 5 6 7 8 9 P Cleared by software Received address is read from SSP1BUF Data to transmit is loaded into SSP1BUF BF is automatically cleared after 8th falling edge of SCL When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK Masters not ACK is copied to ACKSTAT R/W is copied from the matching address byte
SDA
R/W = 1 Automatic A7 A6 A5 A4 A3 A2 A1 ACK
SCL
S
1
SSP1IF
BF
CKP
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
Preliminary
Indicates an address has been received
ACKSTAT
R/W
D/A
S
2010 Microchip Technology Inc.
P
PIC12F/LF1822/16F/LF1823
24.5.3.3 7-bit Transmission with Address Hold Enabled
Setting the AHEN bit of the SSP1CON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSP1IF interrupt is set. Figure 24-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. Bus starts Idle. Master sends Start condition; the S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line the CKP bit is cleared and SSP1IF interrupt is generated. 4. Slave software clears SSP1IF. 5. Slave software reads ACKTIM bit of SSP1CON3 register, and R/W and D/A of the SSP1STAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSP1BUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets ACKDT bit of the SSP1CON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSP1IF after the ACK if the R/W bit is set. 11. Slave software clears SSP1IF. 12. Slave loads value to transmit to the master into SSP1BUF setting the BF bit. Note: SSP1BUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSP1CON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus, allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. 1. 2.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 249
FIGURE 24-19:
DS41413A-page 250
Master releases SDA to slave for ACK sequence R/W = 1 ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 8 9 1 2 3 4 5 6 7 8 9 Automatic Transmitting Data Master sends Stop condition Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK 3 4 5 6 7 P Cleared by software Received address is read from SSP1BUF Data to transmit is loaded into SSP1BUF BF is automatically cleared after 8th falling edge of SCL Slave clears ACKDT to ACK address Master's ACK response is copied to SSP1STAT CKP not cleared When R/W = 1; CKP is always cleared after ACK ACKTIM is cleared on 9th rising edge of SCL Set by software, releases SCL after not ACK
Receiving Address
SDA
A7 A6 A5 A4 A3 A2 A1
SCL
S
1
2
SSP1IF
BF
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
Preliminary
ACKDT
ACKSTAT
CKP
When AHEN = 1; CKP is cleared by hardware after receiving matching address.
ACKTIM
ACKTIM is set on 8th falling edge of SCL
R/W
2010 Microchip Technology Inc.
D/A
PIC12F/LF1822/16F/LF1823
24.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 24.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD This section describes a standard sequence of events for the MSSP1 module configured as an I2C Slave in 10-bit Addressing mode. Figure 24-19 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. Bus starts Idle. Master sends Start condition; S bit of SSP1STAT is set; SSP1IF is set if interrupt-on-Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSP1STAT register is set. Slave sends ACK and SSP1IF is set. Software clears the SSP1IF bit. Software reads received address from SSP1BUF clearing the BF flag. Slave loads low address into SSP1ADD, releasing SCL. Master sends matching low address byte to the Slave; UA bit is set. Note: Updates to the SSP1ADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSP1IF is set. Note: If the low address does not match, SSP1IF and UA are still set so that the slave software can set SSP1ADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSP1IF. 11. Slave reads the received matching address from SSP1BUF clearing BF. 12. Slave loads high address into SSP1ADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSP1IF is set. 14. If SEN bit of SSP1CON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSP1IF. 16. Slave reads the received byte from SSP1BUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSP1ADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 24-20 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 24-21 shows a standard waveform for a slave transmitter in 10-bit Addressing mode.
3. 4. 5. 6. 7. 8.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 251
FIGURE 24-20:
DS41413A-page 252
Master sends Stop condition Receive Second Address Byte Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 0 A9 A8 5 6 7 8 9 1 2 3 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 4 5 6 7 8 9 P SCL is held low while CKP = 0 Cleared by software Receive address is read from SSP1BUF Data is read from SSP1BUF Software updates SSP1ADD and releases SCL
Receive First Address Byte
SDA
1
1
1
1
SCL
S
1
2
3
4
SSP1IF
Set by hardware on 9th falling edge
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
Preliminary
BF
If address matches SSP1ADD it is loaded into SSP1BUF
UA
When UA = 1; SCL is held low
CKP
2010 Microchip Technology Inc.
Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte
FIGURE 24-21:
Receive First Address Byte R/W = 0 A8 ACK ACK A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 Receive Second Address Byte Receive Data
Receive Data D0 ACK D7 D6 D5
SDA
1
1
1
1
0
A9
2010 Microchip Technology Inc.
4 5 6 7 8 9 UA 1 2 9 UA 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1 2 Set by hardware on 9th falling edge Cleared by software Cleared by software SSP1BUF can be read anytime before the next received byte Received data is read from SSP1BUF Update to SSP1ADD is not allowed until 9th falling edge of SCL Update of SSP1ADD, clears UA and releases SCL Set CKP with software releases SCL
SCL
S
1
2
3
SSP1IF
BF
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
PIC12F/LF1822/16F/LF1823
Preliminary
ACKDT
Slave software clears ACKDT to ACK the received byte
UA
CKP
If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared
ACKTIM
DS41413A-page 253
ACKTIM is set by hardware on 8th falling edge of SCL
FIGURE 24-22:
DS41413A-page 254
Master sends Restart event Master sends not ACK Transmitting Data Byte ACK D7 D6 D5 D4 D3 D2 D1 D0 Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK Master sends Stop condition ACK = 1
SDA
Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK
1 1 1 1 0 A9 A8
SCL 5 1 2 Sr 3 4 5 6 78 9 23 4 5 2 6 78 9 6 1 1 7 8 9
S
1
2
3
4
3
4
5
6
7
8
9
P
SSP1IF Cleared by software Set by hardware
Set by hardware
BF Received address is read from SSP1BUF High address is loaded back into SSP1ADD Data to transmit is loaded into SSP1BUF
PIC12F/LF1822/16F/LF1823
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
Preliminary
After SSP1ADD is updated, UA is cleared and SCL is released When R/W = 1; CKP is cleared on 9th falling edge of SCL R/W is copied from the matching address byte
SSP1BUF loaded with received address
UA
UA indicates SSP1ADD must be updated
CKP
ACKSTAT
Set by software releases SCL
Masters not ACK is copied
R/W
D/A
2010 Microchip Technology Inc.
Indicates an address has been received
PIC12F/LF1822/16F/LF1823
24.5.6 CLOCK STRETCHING 24.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSP1CON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 24.5.6.1 Normal Clock Stretching In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSP1ADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 24.5.6.3 Byte NACKing
When AHEN bit of SSP1CON3 is set; CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit of SSP1CON3 is set; CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 24.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT
Following an ACK if the R/W bit of SSP1STAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSP1BUF with data to transfer to the master. If the SEN bit of SSP1CON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSP1BUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSP1BUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests.
Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 24-22).
FIGURE 24-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX - 1
SCL
CKP
Master device asserts clock Master device releases clock
WR SSP1CON1
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 255
PIC12F/LF1822/16F/LF1823
24.5.8 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSP1CON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSP1ADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSP1BUF and respond. Figure 24-23 shows a general call reception sequence. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSP1CON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally.
FIGURE 24-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK
SDA SCL S SSP1IF BF (SSP1STAT<0>)
General Call Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared by software GCEN (SSP1CON2<7>) SSP1BUF is read '1'
24.5.9
SSP1 MASK REGISTER
An SSP1 Mask (SSP1MSK) register (Register 24-5) is available in I2C Slave mode as a mask for the value held in the SSP1SR register during an address comparison operation. A zero (`0') bit in the SSP1MSK register has the effect of making the corresponding bit of the received address a "don't care". This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP1 operation until written with a mask value. The SSP1 Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. * 10-bit Address mode: address compare of A<7:0> only. The SSP1 mask has no effect during the reception of the first (high) byte of the address.
DS41413A-page 256
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.6 I2C MASTER MODE
24.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSP1M bits in the SSP1CON1 register and by setting the SSP1EN bit. In Master mode, the SCL and SDA lines are set as inputs and are manipulated by the MSSP1 hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP1 Interrupt Flag bit, SSP1IF, to be set (SSP1 interrupt, if enabled): * * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP1 module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSP1BUF register to initiate transmission before the Start condition is complete. In this case, the SSP1BUF will not be written to and the WCOL bit will be set, indicating that a write to the SSP1BUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 24.7 "Baud Rate Generator" for more detail.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 257
PIC12F/LF1822/16F/LF1823
24.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 24-25).
FIGURE 24-25:
SDA
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX SCL deasserted but slave holds SCL low (clock arbitration) DX - 1 SCL allowed to transition high
SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h
SCL is sampled high, reload takes place and BRG starts its count BRG Reload
24.6.3
WCOL STATUS FLAG
If the user writes the SSP1BUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Any time the WCOL bit is set it indicates that an action on SSP1BUF was attempted while the module was not Idle. Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSP1CON2 is disabled until the Start condition is complete.
DS41413A-page 258
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.6.4 I2C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSP1CON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSP1STAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSP1ADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSP1CON2
register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCL1IF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start.
FIGURE 24-26:
FIRST START BIT TIMING
Write to SEN bit occurs here SDA = 1, SCL = 1 TBRG SDA TBRG Set S bit (SSP1STAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSP1IF bit Write to SSP1BUF occurs here 1st bit TBRG SCL S TBRG 2nd bit
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 259
PIC12F/LF1822/16F/LF1823
24.6.5 I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit of the SSP1CON2 register is programmed high and the Master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the
SSP1CON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSP1STAT register will be set. The SSP1IF bit will not be set until the Baud Rate Generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'.
FIGURE 24-27:
REPEAT START CONDITION WAVEFORM
Write to SSP1CON2 occurs here SDA = 1, SCL (no change) TBRG SDA S bit set by hardware SDA = 1, SCL = 1 TBRG TBRG 1st bit At completion of Start bit, hardware clears RSEN bit and sets SSP1IF
Write to SSP1BUF occurs here TBRG SCL Sr Repeated Start TBRG
DS41413A-page 260
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.6.6 I2C MASTER MODE TRANSMISSION
24.6.6.3
ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSP1BUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSP1IF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSP1BUF, leaving SCL low and SDA unchanged (Figure 24-27). After the write to the SSP1BUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSP1CON2 register. Following the falling edge of the ninth clock transmission of the address, the SSP1IF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSP1BUF takes place, holding SCL low and allowing SDA to float.
In Transmit mode, the ACKSTAT bit of the SSP1CON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 24.6.6.4 1. 2. 3. 4. 5. 6. Typical transmit sequence:
7.
8.
9. 10. 11.
12. 13.
24.6.6.1
BF Status Flag
The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. The MSSP1 module will wait the required start time before any other operation takes place. The user loads the SSP1BUF with the slave address to transmit. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. The user loads the SSP1BUF with eight bits of data. Data is shifted out the SDA pin until all 8 bits are transmitted. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSP1CON2 register. Interrupt is generated once the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSP1STAT register is set when the CPU writes to SSP1BUF and is cleared when all 8 bits are shifted out.
24.6.6.2
WCOL Status Flag
If the user writes the SSP1BUF when a transmit is already in progress (i.e., SSP1SR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared by software before the next transmission.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 261
FIGURE 24-28:
DS41413A-page 262
Write SSP1CON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSP1CON2<6>
R/W = 0
ACKSTAT in SSP1CON2 = 1
SEN = 0 Transmit Address to Slave SDA A7 SSP1BUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSP1IF 2 3 4 5 6 7 8 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0
ACK
9
P
SSP1IF Cleared by software Cleared by software service routine from SSP1 interrupt Cleared by software
PIC12F/LF1822/16F/LF1823
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Preliminary
BF (SSP1STAT<0>) SSP1BUF written SEN After Start condition, SEN cleared by hardware PEN R/W
SSP1BUF is written by software
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.6.7 I2C MASTER MODE RECEPTION
24.6.7.4 1. 2. 3. 4. 5. Typical Receive Sequence: Master mode reception is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP1 module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The user generates a Start condition by setting the SEN bit of the SSP1CON2 register. SSP1IF is set by hardware on completion of the Start. SSP1IF is cleared by software. User writes SSP1BUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all 8 bits are transmitted. Transmission begins as soon as SSP1BUF is written to. The MSSP1 module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSP1CON2 register. The MSSP1 module generates an interrupt at the end of the ninth clock cycle by setting the SSP1IF bit. User sets the RCEN bit of the SSP1CON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCL, SSP1IF and BF are set. Master clears SSP1IF and reads the received byte from SSP1UF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSP1CON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the Slave and SSP1IF is set. User clears SSP1IF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication.
The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSP1SR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSP1SR are loaded into the SSP1BUF, the BF flag bit is set, the SSP1IF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP1 is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSP1CON2 register.
6.
7.
8. 9. 10. 11.
24.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSP1BUF from SSP1SR. It is cleared when the SSP1BUF register is read.
24.6.7.2
SSP1OV Status Flag
12. 13. 14. 15.
In receive operation, the SSP1OV bit is set when 8 bits are received into the SSP1SR and the BF flag bit is already set from a previous reception.
24.6.7.3
WCOL Status Flag
If the user writes the SSP1BUF when a receive is already in progress (i.e., SSP1SR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 263
FIGURE 24-29:
DS41413A-page 264
Write to SSP1CON2<4> to start Acknowledge sequence SDA = ACKDT (SSP1CON2<5>) = 0 ACK from Master SDA = ACKDT = 0 RCEN = 1, start next receive RCEN cleared automatically Receiving Data from Slave ACK PEN bit = 1 written here Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 R/W = 0 Receiving Data from Slave ACK ACK ACK is not sent Bus master terminates transfer
Write to SSP1CON2<0>(SEN = 1), begin Start condition
Master configured as a receiver by programming SSP1CON2<3> (RCEN = 1) SEN = 0 Write to SSP1BUF occurs here, RCEN cleared ACK from Slave automatically start XMIT
Transmit Address to Slave
SDA D0
A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0
A6 A5 A4 A3 A2
SCL
Data shifted in on falling edge of CLK Set SSP1IF interrupt at end of receive Set SSP1IF interrupt at end of Acknowledge sequence Cleared by software
S
1 5 1 2 3 4 5 1 2 3 4 5 6 7 8
2
3 4 6 8 6 7 8 9
7 9
9
Set SSP1IF at end of receive
P
Set SSP1IF interrupt at end of Acknowledge sequence
SSP1IF
Cleared by software Cleared by software
PIC12F/LF1822/16F/LF1823
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Preliminary
Last bit is shifted into SSP1SR and contents are unloaded into SSP1BUF Master configured as a receiver by programming SSP1CON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDA\ = ACKDT = 0
SDA = 0, SCL = 1 while CPU responds to SSP1IF
Cleared by software
Cleared in software
Set P bit (SSP1STAT<4>) and SSP1IF
BF (SSP1STAT<0>)
SSP1OV
SSP1OV is set because SSP1BUF is still full
ACKEN
RCEN
2010 Microchip Technology Inc.
RCEN cleared automatically
PIC12F/LF1822/16F/LF1823
24.6.8 ACKNOWLEDGE SEQUENCE TIMING 24.6.9 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSP1CON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP1 module then goes into Idle mode (Figure 24-29). A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSP1CON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSP1STAT register is set. A TBRG later, the PEN bit is cleared and the SSP1IF bit is set (Figure 24-30).
24.6.9.1
WCOL Status Flag
24.6.8.1
WCOL Status Flag
If the user writes the SSP1BUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes the SSP1BUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 24-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, write to SSP1CON2 ACKEN = 1, ACKDT = 0 TBRG SDA SCL D0 8 ACK TBRG ACKEN automatically cleared
9
SSP1IF SSP1IF set at the end of receive Note: TBRG = one Baud Rate Generator period. Cleared in software SSP1IF set at the end of Acknowledge sequence
Cleared in software
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Preliminary
DS41413A-page 265
PIC12F/LF1822/16F/LF1823
FIGURE 24-31: STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSP1STAT<4>) is set. PEN bit (SSP1CON2<2>) is cleared by hardware and the SSP1IF bit is set TBRG Write to SSP1CON2, set PEN Falling edge of 9th clock SCL
SDA
ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
24.6.10
SLEEP OPERATION
the I2C slave
24.6.13
While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP1 interrupt is enabled).
MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION
24.6.11
EFFECTS OF A RESET
A Reset disables the MSSP1 module and terminates the current transfer.
24.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP1 module is disabled. Control of the I 2C bus may be taken when the P bit of the SSP1STAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCL1IF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCL1IF, and reset the I2C port to its Idle state (Figure 24-31). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSP1BUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSP1CON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSP1IF bit will be set. A write to the SSP1BUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSP1STAT register, or the bus is Idle and the S and P bits are cleared.
DS41413A-page 266
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 24-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCL = 0 SDA line pulled low by another source SDA released by master SDA Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred.
SCL
Set bus collision interrupt (BCL1IF)
BCL1IF
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Preliminary
DS41413A-page 267
PIC12F/LF1822/16F/LF1823
24.6.13.1 Bus Collision During a Start Condition
During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 24-32). SCL is sampled low before SDA is asserted low (Figure 24-33). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 24-34). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions.
During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCL1IF flag is set and * the MSSP1 module is reset to its Idle state (Figure 24-32). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition.
FIGURE 24-33:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set. Set BCL1IF, S bit and SSP1IF set because SDA = 0, SCL = 1.
SDA
SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN SDA sampled low before Start condition. Set BCL1IF. S bit and SSP1IF set because SDA = 0, SCL = 1. SSP1IF and BCL1IF are cleared by software S SEN cleared automatically because of bus collision. SSP1 module reset into Idle state.
BCL1IF
SSP1IF SSP1IF and BCL1IF are cleared by software
DS41413A-page 268
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 24-34: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCL1IF. SCL = 0 before BRG time-out, bus collision occurs. Set BCL1IF. BCL1IF Interrupt cleared by software S
SCL
SEN
'0'
'0' '0'
SSP1IF '0'
FIGURE 24-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1 Set S Less than TBRG
TBRG
Set SSP1IF
SDA
SDA pulled low by other master. Reset BRG and assert SDA. S SCL pulled low after BRG time-out Set SEN, enable Start sequence if SDA = 1, SCL = 1
SCL
SEN
BCL1IF
'0'
S
SSP1IF SDA = 0, SCL = 1, set SSP1IF Interrupts cleared by software
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Preliminary
DS41413A-page 269
PIC12F/LF1822/16F/LF1823
24.6.13.2 Bus Collision During a Repeated Start Condition
During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 24-35). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 24-36. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete.
When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSP1ADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled.
FIGURE 24-36:
SDA
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SCL Sample SDA when SCL goes high. If SDA = 0, set BCL1IF and release SDA and SCL. RSEN
BCL1IF Cleared by software S SSP1IF
'0' '0'
FIGURE 24-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA SCL SCL goes low before SDA, set BCL1IF. Release SDA and SCL. Interrupt cleared by software RSEN S SSP1IF
BCL1IF
'0'
DS41413A-page 270
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.6.13.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if: a) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is deasserted, SCL is sampled low before SDA goes high. The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSP1ADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 24-37). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 24-38).
b)
FIGURE 24-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG SDA sampled low after TBRG, set BCL1IF
SDA SDA asserted low SCL PEN BCL1IF P SSP1IF
'0' '0'
FIGURE 24-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA Assert SDA SCL PEN BCL1IF P SSP1IF SCL goes low before SDA goes high, set BCL1IF
'0' '0'
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Preliminary
DS41413A-page 271
PIC12F/LF1822/16F/LF1823
TABLE 24-3:
Name INTCON PIE1 PIE2 PIR1 PIR2 SSP1ADD SSP1BUF SSP1CON1 SSP1CON2 SSP1CON3 SSP1MSK SSP1STAT TRISA TRISC Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH I2CTM OPERATION
Bit 7 GIE Bit 6 PEIE ADIE C2IE(1) ADIF C2IF(1) ADD6 SSPOV ACKSTAT PCIE MSK6 CKE -- -- Bit 5 TMR0IE RCIE C1IE RCIF C1IF ADD5 SSPEN ACKDT SCIE MSK5 D/A TRISA5 TRISC5 Bit 4 INTE TXIE EEIE TXIF EEIF ADD4 CKP ACKEN BOEN MSK4 P TRISA4 TRISC4 RCEN SDAHT MSK3 S TRISA3 TRISC3 Bit 3 IOCIE SSP1IE BCL1IE SSP1IF BCL1IF ADD3 Bit 2 TMR0IF CCP1IE -- CCP1IF -- ADD2 Bit 1 INTF TMR2IE -- TMR2IF -- ADD1 -- ADD0 Bit 0 IOCIF TMR1IE -- Reset Values on Page 89 90 91 92 93 278 229* SSPM<3:0> PEN SBCDE MSK2 R/W TRISA2 TRISC2 RSEN AHEN MSK1 UA TRISA1 TRISC1 SEN DHEN MSK0 BF TRISA0 TRISC0 275 276 277 278 274 121 125
TMR1GIE OSFIE TMR1GIF OSFIF ADD7 WCOL GCEN ACKTIM MSK7 SMP -- --
Synchronous Serial Port Receive Buffer/Transmit Register
-- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I2CTM mode. Page provides register information. PIC16F/LF1823 only.
DS41413A-page 272
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
24.7 BAUD RATE GENERATOR
The MSSP1 module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSP1ADD register (Register 24-6). When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal "Reload" in Figure 24-39 triggers the value from SSP1ADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP1 is being operated in. Table 24-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSP1ADD.
EQUATION 24-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4
FIGURE 24-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSP1M<3:0> SSP1ADD<7:0>
SSP1M<3:0> SCL
Reload Control SSP1CLK
Reload
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid for SSP1ADD when used as a Baud Rate Generator for I2C. This is an implementation limitation.
TABLE 24-4:
FOSC
MSSP1 CLOCK RATE W/BRG
FCY 8 MHz 8 MHz 8 MHz 4 MHz 4 MHz 4 MHz 1 MHz I2C BRG Value 13h 19h 4Fh 09h 0Ch 27h 09h FCLOCK (2 Rollovers of BRG) 400 kHz(1) 308 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 100 kHz
32 MHz 32 MHz 32 MHz 16 MHz 16 MHz 16 MHz 4 MHz Note 1:
2C
specification (which applies to rates greater than The I interface does not conform to the 400 kHz 100 kHz) in all details, but may be used with care where higher rates are required by the application.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 273
PIC12F/LF1822/16F/LF1823
REGISTER 24-1:
R/W-0/0 SMP bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 CTM mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP1 is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSP1ADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSP1BUF is full 0 = Receive not complete, SSP1BUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSP1STAT: SSP1 STATUS REGISTER
R/W-0/0 CKE R-0/0 D/A R-0/0 P R-0/0 S R-0/0 R/W R-0/0 UA R-0/0 BF bit 0
bit 4
bit 0
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REGISTER 24-2:
R/C/HS-0/0 WCOL bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HS = Bit is set by hardware C = User cleared
SSP1CON1: SSP1 CONTROL REGISTER 1
R/W-0/0 SSP1EN R/W-0/0 CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 SSP1M<3:0>
R/C/HS-0/0 SSP1OV
WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSP1OV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSP1BUF register is still holding the previous data. In case of overflow, the data in SSP1SR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register (must be cleared in software). 0 = No overflow In I2 C mode: 1 = A byte is received while the SSP1BUF register is still holding the previous byte. SSP1OV is a "don't care" in Transmit mode (must be cleared in software). 0 = No overflow SSP1EN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode: Unused in this mode SSP1M<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) 1001 = Reserved 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1)) 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1: 2: 3: 4: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. When enabled, these pins must be properly configured as input or output. When enabled, the SDA and SCL pins must be configured as inputs. SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode.
bit 6
bit 5
bit 4
bit 3-0
Note
2010 Microchip Technology Inc.
Preliminary
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REGISTER 24-3:
R/W-0/0 GCEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets HC = Cleared by hardware S = User set
SSP1CON2: SSP1 CONTROL REGISTER 2
R-0/0 R/W-0/0 ACKDT R/S/HS-0/0 ACKEN R/S/HS-0/0 RCEN R/S/HS-0/0 PEN R/S/HS-0/0 RSEN R/W/HS-0/0 SEN bit 0
ACKSTAT
GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 24-4:
R-0/0 ACKTIM bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the SSP1CON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSP1OV bit only if the BF bit = 0. 0 = SSP1BUF is only updated when SSP1OV is clear SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the SSP1CON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSP1CON1 register and SCL is held low. 0 = Data holding is disabled For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSP1CON3: SSP1 CONTROL REGISTER 3
R/W-0/0 SCIE R/W-0/0 BOEN R/W-0/0 SDAHT R/W-0/0 SBCDE R/W-0/0 AHEN R/W-0/0 DHEN bit 0 PCIE
R/W-0/0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 0
Note 1:
2: 3:
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Preliminary
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REGISTER 24-5:
R/W-1/1 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-1 W = Writable bit x = Bit is unknown `0' = Bit is cleared MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSP1ADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
SSP1MSK: SSP1 MASK REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 bit 0 MSK<7:0>
R/W-1/1
bit 0
REGISTER 24-6:
R/W-0/0 bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set Master mode: bit 7-0
SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 bit 0 ADD<7:0>
R/W-0/0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode -- Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a "don't care". Bit pattern sent by master is fixed by I2C specification and must be equal to `11110'. However, those bits are compared by hardware and are not affected by the value in this register. ADD<2:1>: Two Most Significant bits of 10-bit address Not used: Unused in this mode. Bit state is a "don't care".
bit 2-1 bit 0
10-Bit Slave mode -- Least Significant Address byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode: bit 7-1 bit 0 ADD<7:1>: 7-bit address Not used: Unused in this mode. Bit state is a "don't care".
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
25.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The EUSART module includes the following capabilities: Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 25-1 and Figure 25-2. * * * * * * * * * *
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device.
FIGURE 25-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIE TXIF LSb Interrupt
TXREG Register 8 MSb (8)
TX/CK pin Pin Buffer and Control
***
Transmit Shift Register (TSR)
0
TXEN Baud Rate Generator BRG16 +1 SPBRGH SPBRGL Multiplier SYNC BRGH BRG16 TRMT FOSC /n n x4 x16 x64 0 0 0 1X00 X110 X101 TX9D TX9 SPEN
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Preliminary
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PIC12F/LF1822/16F/LF1823
FIGURE 25-2: EUSART RECEIVE BLOCK DIAGRAM
SPEN CREN OERR RCIDL
RX/DT pin Pin Buffer and Control Baud Rate Generator BRG16 +1 SPBRGH SPBRGL Multiplier SYNC BRGH BRG16 x4 x16 x64 0 0 0 FERR 1X00 X110 X101 FOSC Data Recovery
MSb Stop (8) 7
RSR Register
LSb 0 START
***
RX9
1
/n
n FIFO
RX9D
RCREG Register 8
Data Bus RCIF RCIE Interrupt
The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These registers are detailed in Register 25-1, Register 25-2 and Register 25-3, respectively. When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output.
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PIC12F/LF1822/16F/LF1823
25.1 EUSART Asynchronous Mode
25.1.1.2 Transmitting Data
The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a `1' data bit, and a VOL space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is 8 bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 25-5 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG.
25.1.1.3
Transmit Interrupt Flag
25.1.1
EUSART ASYNCHRONOUS TRANSMITTER
The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG.
The EUSART transmitter block diagram is shown in Figure 25-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register.
25.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the TX/CK I/O pin as an output. Note 1: The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set.
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Preliminary
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25.1.1.4 TSR Status 25.1.1.6
1.
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: The TSR register is not mapped in data memory, so it is not available to the user.
2. 3.
25.1.1.5
Transmitting 9-Bit Characters
4.
The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift 9 bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant, data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the 8 Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 25.1.2.7 "Address Detection" for more information on the address mode.
5.
6. 7.
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the 8 Least Significant data bits are an address when the receiver is set for address detection. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission.
FIGURE 25-3:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg.
FIGURE 25-4:
Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
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TABLE 25-1:
Name BAUDCON INTCON PIE1 PIR1 RCSTA SPBRGL SPBRGH TRISA TRISC(1) TXREG TXSTA
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 -- -- CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 -- -- TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISA5 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISA4 TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN BRG3 BRG11 TRISA3 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISA2 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISA1 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISA0 TRISC0 TX9D Register on Page 290 89 90 92 289 291* 291* 121 125 281* 288
EUSART Transmit Data Register
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Transmission. * Page provides register information. Note 1: PIC16F/LF1823 only.
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Preliminary
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25.1.2 EUSART ASYNCHRONOUS RECEIVER 25.1.2.2 Receiving Data
The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 25-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all 8 or 9 bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 25.1.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 25.1.2.5 "Receive Overrun Error" for more information on overrun errors.
25.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the TX/CK I/O pin as an input. Note 1: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function.
25.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: * RCIE interrupt enable bit of the PIE1 register * PEIE peripheral interrupt enable bit of the INTCON register * GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits.
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25.1.2.4 Receive Framing Error 25.1.2.7 Address Detection
Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit.
25.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register.
25.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the EUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
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25.1.2.8
1.
Asynchronous Reception Set-up:
25.1.2.9
9-bit Address Detection Mode Set-up
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received 8 Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts.
FIGURE 25-5:
RX/DT pin Rcv Shift Reg Rcv Buffer Reg. RCIDL Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
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TABLE 25-2:
Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRGL SPBRGH TRISA TRISC
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 -- -- CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 -- -- TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISA5 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISA4 TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN BRG3 BRG11 TRISA3 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISA2 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISA1 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISA0 TRISC0 TX9D Register on Page 290 89 90 92 284* 289 291* 291* 121 125 288
EUSART Receive Data Register
TXSTA
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Asynchronous Reception. * Page provides register information. Note 1: PIC16F/LF1823 only.
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25.2 Clock Accuracy with Asynchronous Operation
The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 5.2.2 "Internal Clock Sources" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 25.3.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency.
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind.
REGISTER 25-1:
R/W-/0 CSRC bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0/0 TX9 R/W-0/0 TXEN(1) R/W-0/0 SYNC R/W-0/0 SENDB R/W-0/0 BRGH R-1/1 TRMT R/W-0/0 TX9D bit 0
W = Writable bit x = Bit is unknown `0' = Bit is cleared
U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 25-2:
R/W-0/0 SPEN bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0/0 SREN R/W-0/0 CREN R/W-0/0 ADDEN R-0/0 FERR R-0/0 OERR R-x/x RX9D bit 0 RX9
R/W-0/0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 25-3:
R-0/0 ABDOVF bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care Unimplemented: Read as `0' SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data 0 = Transmit non-inverted data Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
BAUDCON: BAUD RATE CONTROL REGISTER
R-1/1 RCIDL U-0 -- R/W-0/0 SCKP R/W-0/0 BRG16 U-0 -- R/W-0/0 WUE R/W-0/0 ABDEN bit 0
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
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25.3 EUSART Baud Rate Generator (BRG)
EXAMPLE 25-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
FOSC Desired Baud Rate = ----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1
The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 25-3 contains the formulas for determining the baud rate. Example 25-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 25-3. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock.
Solving for SPBRGH:SPBRGL:
FOSC -------------------------------------------Desired Baud Rate X = --------------------------------------------- - 1 64 16000000 ----------------------9600 = ----------------------- - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = -------------------------64 25 + 1 = 9615 Calc. Baud Rate - Desired Baud Rate Error = ------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600
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TABLE 25-3:
SYNC 0 0 0 0 1 1 Legend:
BAUD RATE FORMULAS
BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n+1)] Baud Rate Formula FOSC/[64 (n+1)] FOSC/[16 (n+1)]
Configuration Bits
x = Don't care, n = value of SPBRGH, SPBRGL register pair
TABLE 25-4:
Name BAUDCON RCSTA SPBRGL SPBRGH TXSTA
SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Bit 7 ABDOVF SPEN BRG7 BRG15 CSRC Bit 6 RCIDL RX9 BRG6 BRG14 TX9 Bit 5 -- SREN BRG5 BRG13 TXEN Bit 4 SCKP CREN BRG4 BRG12 SYNC Bit 3 BRG16 ADDEN BRG3 BRG11 SENDB Bit 2 -- FERR BRG2 BRG10 BRGH Bit 1 WUE OERR BRG1 BRG9 TRMT Bit 0 ABDEN RX9D BRG0 BRG8 TX9D Register on Page 290 289 291* 291* 288
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information.
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate -- 1221 2404 9470 10417 19.53k -- -- % Error -- 1.73 0.16 -1.36 0.00 1.73 -- -- SPBRG value (decimal) -- 255 129 32 29 15 -- -- FOSC = 18.432 MHz Actual Rate -- 1200 2400 9600 10286 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -1.26 0.00 0.00 -- SPBRG value (decimal) -- 239 119 29 27 14 7 -- FOSC = 11.0592 MHz Actual Rate -- 1200 2400 9600 10165 19.20k 57.60k -- % Error -- 0.00 0.00 0.00 -2.42 0.00 0.00 -- SPBRG value (decimal) -- 143 71 17 16 8 2 --
FOSC = 32.000 MHz Actual Rate -- -- 2404 9615 10417 19.23k 55.55k -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 3 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate -- 1202 2404 9615 10417 -- -- -- % Error -- 0.16 0.16 0.16 0.00 -- -- -- SPBRG value (decimal) -- 103 51 12 11 -- -- -- FOSC = 4.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- -- FOSC = 3.6864 MHz Actual Rate 300 1200 2400 9600 -- 19.20k 57.60k -- % Error 0.00 0.00 0.00 0.00 -- 0.00 0.00 -- SPBRG value (decimal) 191 47 23 5 -- 2 0 -- FOSC = 1.000 MHz Actual Rate 300 1202 -- -- -- -- -- -- % Error 0.16 0.16 -- -- -- -- -- -- SPBRG value (decimal) 51 12 -- -- -- -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 57.14k 117.64k % Error -- -- -- 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) -- -- -- 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate -- -- -- 9615 10417 19.23k 56.82k 113.64k % Error -- -- -- 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) -- -- -- 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate -- -- -- 9600 10378 19.20k 57.60k 115.2k % Error -- -- -- 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate -- -- -- 9600 10473 19.20k 57.60k 115.2k % Error -- -- -- 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- -- -- 71 65 35 11 5
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0 FOSC = 4.000 MHz Actual Rate -- 1202 2404 9615 10417 19.23k -- -- % Error -- 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) -- 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate -- 1200 2400 9600 10473 19.2k 57.60k 115.2k % Error -- 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) -- 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
FOSC = 8.000 MHz Actual Rate -- -- 2404 9615 10417 19231 55556 -- % Error -- -- 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) -- -- 207 51 47 25 8 --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 -0.04 0.16 0.00 0.16 -0.79 2.12 SPBRG value (decimal) 6666 3332 832 207 191 103 34 16 FOSC = 20.000 MHz Actual Rate 300.0 1200 2399 9615 10417 19.23k 56.818 113.636 % Error -0.01 -0.03 -0.03 0.16 0.00 0.16 -1.36 -1.36 SPBRG value (decimal) 4166 1041 520 129 119 64 21 10 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10378 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 -0.37 0.00 0.00 0.00 SPBRG value (decimal) 3839 959 479 119 110 59 19 9 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 2303 575 287 71 65 35 11 5
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 299.9 1199 2404 9615 10417 19.23k 55556 -- % Error -0.02 -0.08 0.16 0.16 0.00 0.16 -3.55 -- SPBRG value (decimal) 1666 416 207 51 47 25 8 -- FOSC = 4.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- -- FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 767 191 95 23 21 11 3 1 FOSC = 1.000 MHz Actual Rate 300.5 1202 2404 -- 10417 -- -- -- % Error 0.16 0.16 0.16 -- 0.00 -- -- -- SPBRG value (decimal) 207 51 25 -- 5 -- -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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TABLE 25-5:
BAUD RATE
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 20.000 MHz Actual Rate 300.0 1200 2400 9597 10417 19.23k 57.47k 116.3k % Error 0.00 -0.01 0.02 -0.03 0.00 0.16 -0.22 0.94 SPBRG value (decimal) 16665 4166 2082 520 479 259 86 42 FOSC = 18.432 MHz Actual Rate 300.0 1200 2400 9600 10425 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.08 0.00 0.00 0.00 SPBRG value (decimal) 15359 3839 1919 479 441 239 79 39 FOSC = 11.0592 MHz Actual Rate 300.0 1200 2400 9600 10433 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.16 0.00 0.00 0.00 SPBRG value (decimal) 9215 2303 1151 287 264 143 47 23
FOSC = 32.000 MHz Actual Rate 300.0 1200 2400 9604 10417 19.18k 57.55k 115.9k % Error 0.00 0.00 0.01 0.04 0.00 -0.08 -0.08 0.64 SPBRG value (decimal) 26666 6666 3332 832 767 416 138 68
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate 300.0 1200 2401 9615 10417 19.23k 57.14k 117.6k % Error 0.00 -0.02 0.04 0.16 0 0.16 -0.79 2.12 SPBRG value (decimal) 6666 1666 832 207 191 103 34 16 FOSC = 4.000 MHz Actual Rate 300.0 1200 2398 9615 10417 19.23k 58.82k 111.1k % Error 0.01 0.04 0.08 0.16 0.00 0.16 2.12 -3.55 SPBRG value (decimal) 3332 832 416 103 95 51 16 8 FOSC = 3.6864 MHz Actual Rate 300.0 1200 2400 9600 10473 19.20k 57.60k 115.2k % Error 0.00 0.00 0.00 0.00 0.53 0.00 0.00 0.00 SPBRG value (decimal) 3071 767 383 95 87 47 15 7 FOSC = 1.000 MHz Actual Rate 300.1 1202 2404 9615 10417 19.23k -- -- % Error 0.04 0.16 0.16 0.16 0.00 0.16 -- -- SPBRG value (decimal) 832 207 103 25 23 12 -- --
300 1200 2400 9600 10417 19.2k 57.6k 115.2k
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PIC12F/LF1822/16F/LF1823
25.3.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence (Figure 25-6). While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Table 25-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 25-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 25.3.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at 1. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair.
TABLE 25-6:
BRG16 0 0 1 1 Note: BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Base Clock FOSC/64 FOSC/16 FOSC/16 FOSC/4 BRG ABD Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of BRG16 setting.
FIGURE 25-6:
BRG Value RX pin BRG Clock Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL SPBRGH Note 1:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh 0000h Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit
Auto Cleared
XXh XXh The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
1Ch 00h
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PIC12F/LF1822/16F/LF1823
25.3.2 AUTO-BAUD OVERFLOW 25.3.3.1 Special Considerations
During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin. Upon detecting the fifth RX edge, the hardware will set the RCIF interrupt flag and clear the ABDEN bit of the BAUDCON register. The RCIF flag can be subsequently cleared by reading the RCREG register. The ABDOVF flag of the BAUDCON register can be cleared by software directly. To terminate the auto-baud process before the RCIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be 10 or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Startup Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
25.3.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 25-7), and asynchronously if the device is in Sleep mode (Figure 25-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 297
PIC12F/LF1822/16F/LF1823
FIGURE 25-7:
OSC1 WUE bit RX/DT Line RCIF Note 1: The EUSART remains in Idle while the WUE bit is set.
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit set by user Auto Cleared
Cleared due to User Read of RCREG
FIGURE 25-8:
OSC1
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Auto Cleared
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Bit Set by User WUE bit RX/DT Line RCIF Sleep Command Executed Note 1: 2:
Note 1 Sleep Ends Cleared due to User Read of RCREG
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
DS41413A-page 298
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
25.3.4 BREAK CHARACTER SEQUENCE 25.3.5 RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 25-9 for the timing of the Break character sequence. The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the Received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCIF bit is set * FERR bit is set * RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 25.3.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode.
25.3.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
FIGURE 25-9:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start bit
bit 0
bit 1 Break
bit 11
Stop bit
TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit)
SENDB Sampled Here
Auto Cleared
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Preliminary
DS41413A-page 299
PIC12F/LF1822/16F/LF1823
25.4 EUSART Synchronous Mode
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock.
25.4.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user.
25.4.1
SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART for Synchronous Master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1
25.4.1.4
1.
Synchronous Master Transmission Set-up:
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART.
2. 3. 4. 5. 6.
25.4.1.1
Master Clock
7. 8.
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits.
Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 25.3 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register.
25.4.1.2
Clock Polarity
A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock.
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 25-10:
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit Write Word 1 Write Word 2
SYNCHRONOUS TRANSMISSION
bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7
TXEN bit Note:
`1' Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
`1'
FIGURE 25-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7
TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 25-7:
Name BAUDCON INTCON PIE1 PIR1 RCSTA SPBRGL SPBRGH TRISC(1) TXREG TXSTA Legend: * Note 1:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 -- CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 -- TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN BRG3 BRG11 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 TX9D Register on Page 290 89 90 92 289 291* 291* 125 281* 288
EUSART Transmit Data Register -- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Master Transmission. Page provides register information. PIC16F/LF1823 only.
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Preliminary
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PIC12F/LF1822/16F/LF1823
25.4.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
25.4.1.8
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set, the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
25.4.1.9
1.
Synchronous Master Reception Set-up:
25.4.1.6
Slave Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared.
Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
25.4.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters
DS41413A-page 302
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 25-12:
RX/DT pin TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. `0'
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TABLE 25-8:
Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA SPBRGL SPBRGH TRISC
(1)
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN BRG7 BRG15 -- CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 BRG6 BRG14 -- TX9 Bit 5 -- TMR0IE RCIE RCIF SREN BRG5 BRG13 TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN BRG4 BRG12 TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN BRG3 BRG11 TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR BRG2 BRG10 TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR BRG1 BRG9 TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D BRG0 BRG8 TRISC0 TX9D Register on Page 290 89 90 92 284* 289 291* 291* 125 288
EUSART Receive Data Register
TXSTA
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Master Reception. * Page provides register information. Note 1: PIC16F/LF1823 only.
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Preliminary
DS41413A-page 303
PIC12F/LF1822/16F/LF1823
25.4.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART for Synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. The first character will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART.
5.
25.4.2.2
1. 2. 3. 4.
Synchronous Slave Transmission Set-up:
25.4.2.1
EUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (see Section 25.4.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode.
5. 6. 7. 8.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant 8 bits to the TXREG register.
TABLE 25-9:
Name BAUDCON INTCON PIE1 PIR1 RCSTA TRISC(1) TXREG TXSTA
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 ABDOVF GIE TMR1GIE TMR1GIF SPEN -- CSRC Bit 6 RCIDL PEIE ADIE ADIF RX9 -- TX9 Bit 5 -- TMR0IE RCIE RCIF SREN TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D TRISC0 TX9D Register on Page 290 89 90 92 289 125 281* 288
EUSART Transmit Data Register
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Slave Transmission. * Page provides register information. Note 1: PIC16F/LF1823 only.
DS41413A-page 304
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
25.4.2.3 EUSART Synchronous Slave Reception 25.4.2.4
1. 2. 3.
Synchronous Slave Reception Set-up:
The operation of the Synchronous Master and Slave modes is identical (Section 25.4.1.5 "Synchronous Master Reception"), with the following exceptions: * Sleep * CREN bit is always set, therefore the receiver is never Idle * SREN bit, which is a "don't care" in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector.
4. 5. 6.
7.
8. 9.
Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name BAUDCON INTCON PIE1 PIR1 RCREG RCSTA TRISC(1) TXSTA SPEN -- CSRC RX9 -- TX9 Bit 7 ABDOVF GIE TMR1GIE TMR1GIF Bit 6 RCIDL PEIE ADIE ADIF Bit 5 -- TMR0IE RCIE RCIF SREN TRISC5 TXEN Bit 4 SCKP INTE TXIE TXIF CREN TRISC4 SYNC Bit 3 BRG16 IOCIE SSP1IE SSP1IF ADDEN TRISC3 SENDB Bit 2 -- TMR0IF CCP1IE CCP1IF FERR TRISC2 BRGH Bit 1 WUE INTF TMR2IE TMR2IF OERR TRISC1 TRMT Bit 0 ABDEN IOCIF TMR1IE TMR1IF RX9D TRISC0 TX9D Register on Page 290 89 90 92 284* 289 125 288
EUSART Receive Data Register
Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for Synchronous Slave Reception. * Page provides register information. Note 1: PIC16F/LF1823 only.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 305
PIC12F/LF1822/16F/LF1823
25.5 EUSART Operation During Sleep
25.5.2
The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock; and therefore, cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.
SYNCHRONOUS TRANSMIT DURING SLEEP
To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Transmission (see Section 25.4.2.2 "Synchronous Slave Transmission Set-up:"). * The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby, filling the TSR and transmit buffer. * If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called.
25.5.1
SYNCHRONOUS RECEIVE DURING SLEEP
To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 25.4.2.4 "Synchronous Slave Reception Set-up:"). * If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. * The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called.
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PIC12F/LF1822/16F/LF1823
26.0 CAPACITIVE SENSING MODULE
The capacitive sensing module allows for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module. The capacitive sensing module requires software and at least one timer resource to determine the change in frequency. Key features of this module include: * * * * * * * Analog MUX for monitoring multiple inputs Capacitive sensing oscillator Multiple Power modes High power range with variable voltage references Multiple timer resources Software control Operation during Sleep
FIGURE 26-1:
CAPACITIVE SENSING BLOCK DIAGRAM
Timer0 Module T0XCS FOSC/4 T0CKI CPSCH<3:0> CPSON(2) CPSRNG<1:0> CPSON Capacitive Sensing Oscillator CPSOSC CPSCLK CPSOUT 0 Ref+ 1 FVR 0 1 0 1 TMR0CS TMR0 Overflow Set TMR0IF
Timer1 Module T1CS<1:0> FOSC FOSC/4 T1OSC/ T1CKI T1GSEL<1:0> T1G SYNCC1OUT SYNCC2OUT Timer1 Gate Control Logic EN TMR1H:TMR1L
CPS0 CPS1 CPS2 CPS3 CPS4(1) CPS5
(1)
Ref-
0 1 DAC
Int. Ref.
CPS6(1) CPS7(1)
CPSRM
Note 1: 2:
Reference CPSCON1 register (Register 26-2) for channels implemented on each device. If CPSON = 0, disabling capacitive sensing, no channel is selected.
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FIGURE 26-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM
Oscillator Module
VDD
(1)
+ CPSx Analog Pin
(1)
(2)
S
(2)
Q
CPSCLK
+
R
Internal References 0 1 0 Ref+ DAC 1 FVR
Ref-
CPSRM
Note 1: 2:
Module Enable and Power mode selections are not shown. Comparators remain active in Noise Detection mode.
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26.1 Analog MUX 26.3 Voltage References
The capacitive sensing module can monitor up to four inputs for the PIC12F/LF1822 (CPSCH<3:0>) and up to eight inputs for the PIC16F/LF1823 (CPSCH<7:0>). See Register 26-2 for details. The capacitive sensing inputs are defined as CPS<7:0>, as applicable to device. To determine if a frequency change has occurred the user must: * Select the appropriate CPS pin by setting the appropriate CPSCH bits of the CPSCON1 register. * Set the corresponding ANSEL bit. * Set the corresponding TRIS bit. * Run the software algorithm. Selection of the CPSx pin while the module is enabled will cause the capacitive sensing oscillator to be on the CPSx pin. Failure to set the corresponding ANSEL and TRIS bits can cause the capacitive sensing oscillator to stop, leading to false frequency readings. The capacitive sensing oscillator uses voltage references to provide two voltage thresholds for oscillation. The upper voltage threshold is referred to as Ref+ and the lower voltage threshold is referred to as Ref-. The user can elect to use fixed voltage references, which are internal to the capacitive sensing oscillator, or variable voltage references, which are supplied by the Fixed Voltage Reference (FVR) module and the Digital-to-Analog Converter (DAC) module. When the fixed voltage references are used, the VSS voltage determines the lower threshold level (Ref-) and the VDD voltage determines the upper threshold level (Ref+). When the variable voltage references are used, the DAC voltage determines the lower threshold level (Ref-) and the FVR voltage determines the upper threshold level (Ref+). An advantage of using these reference sources is that oscillation frequency remains constant with changes in VDD. Different oscillation frequencies can be obtained through the use of these variable voltage references. The more the upper voltage reference level is lowered and the more the lower voltage reference level is raised, the higher the capacitive sensing oscillator frequency becomes. Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. Setting this bit selects the variable voltage references and clearing this bit selects the fixed voltage references. Please see Section 14.0 "Fixed Voltage Reference (FVR)" and Section 16.0 "Digital-to-Analog Converter (DAC) Module" for more information on configuring the variable voltage levels.
26.2
Capacitive Sensing Oscillator
The capacitive sensing oscillator consists of a constant current source and a constant current sink, to produce a triangle waveform. The CPSOUT bit of the CPSCON0 register shows the status of the capacitive sensing oscillator, whether it is a sinking or sourcing current. The oscillator is designed to drive a capacitive load (single PCB pad) and at the same time, be a clock source to either Timer0 or Timer1. The oscillator has three different current settings as defined by CPSRNG<1:0> of the CPSCON0 register. The different current settings for the oscillator serve two purposes: * Maximize the number of counts in a timer for a fixed time base. * Maximize the count differential in the timer during a change in frequency.
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26.4 Power Modes
The capacitive sensing oscillator can operate in one of seven different power modes. The power modes are separated into two ranges; the low range and the high range. When the oscillator's low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. When the oscillator's high range is selected, the variable voltage references supplied by the FVR and DAC modules are being used. Selection between the voltage references is controlled by the CPSRM bit of the CPSCON0 register. See Section 26.3 "Voltage References" for more information. Within each range there are three distinct Power modes; low, medium and high. Current consumption is dependent upon the range and mode selected. Selecting Power modes within each range is accomplished by configuring the CPSRNG <1:0> bits in the CPSCON0 register. See Table 26-1 for proper Power mode selection. The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourcing of current on the analog pin but leaves the rest of the oscillator circuitry active. This reduces the oscillation frequency on the analog pin to zero and also greatly reduces the current consumed by the oscillator module. When noise is introduced onto the pin, the oscillator is driven at the frequency determined by the noise. This produces a detectable signal at the comparator output, indicating the presence of activity on the pin. Figure 26-2 shows a more detailed drawing of the current sources and comparators associated with the oscillator.
TABLE 26-1:
CPSRM
POWER MODE SELECTION
Range CPSRNG<1:0> 00 01 10 11 00 01 10 11 Mode Off Low Medium High Noise Detection Low Medium High Nominal Current(1) 0.0 A 0.1 A 1.2 A 18 A 0.0 A 9 A 30 A 100 A
0
Low
1
High
Note 1:
See Section 29.0 "Electrical Specifications" for more information.
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26.5 Timer Resources 26.7 Software Control
To measure the change in frequency of the capacitive sensing oscillator, a fixed time base is required. For the period of the fixed time base, the capacitive sensing oscillator is used to clock either Timer0 or Timer1. The frequency of the capacitive sensing oscillator is equal to the number of counts in the timer, divided by the period of the fixed time base. The software portion of the capacitive sensing module is required to determine the change in frequency of the capacitive sensing oscillator. This is accomplished by the following: * Setting a fixed time base to acquire counts on Timer0 or Timer1. * Establishing the nominal frequency for the capacitive sensing oscillator. * Establishing the reduced frequency for the capacitive sensing oscillator due to an additional capacitive load. * Set the frequency threshold.
26.6
Fixed Time Base
To measure the frequency of the capacitive sensing oscillator, a fixed time base is required. Any timer resource or software loop can be used to establish the fixed time base. It is up to the end user to determine the method in which the fixed time base is generated. Note: The fixed time base can not be generated by the timer resource that the capacitive sensing oscillator is clocking.
26.7.1
NOMINAL FREQUENCY (NO CAPACITIVE LOAD)
To determine the nominal frequency of the capacitive sensing oscillator: * Remove any extra capacitive load on the selected CPSx pin. * At the start of the fixed time base, clear the timer resource. * At the end of the fixed time base save the value in the timer resource. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator for the given time base. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer, divided by the period of the fixed time base.
26.6.1
TIMER0
To select Timer0 as the timer resource for the capacitive sensing module: * Set the T0XCS bit of the CPSCON0 register. * Clear the TMR0CS bit of the OPTION register. When Timer0 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer0. Refer to Section 19.0 "Timer0 Module" for additional information.
26.6.2
TIMER1
To select Timer1 as the timer resource for the capacitive sensing module, set the TMR1CS<1:0> of the T1CON register to `11'. When Timer1 is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for Timer1. Because the Timer1 module has a gate control, developing a time base for the frequency measurement can be simplified by using the Timer0 overflow flag. It is recommend that the Timer0 overflow flag, in conjunction with the Toggle mode of the Timer1 Gate, be used to develop the fixed time base required by the software portion of the capacitive sensing module. Refer to Section 20.12 "Timer1 Gate Control Register" for additional information.
26.7.2
REDUCED FREQUENCY (ADDITIONAL CAPACITIVE LOAD)
The extra capacitive load will cause the frequency of the capacitive sensing oscillator to decrease. To determine the reduced frequency of the capacitive sensing oscillator: * Add a typical capacitive load on the selected CPSx pin. * Use the same fixed time base as the nominal frequency measurement. * At the start of the fixed time base, clear the timer resource. * At the end of the fixed time base, save the value in the timer resource. The value of the timer resource is the number of oscillations of the capacitive sensing oscillator with an additional capacitive load. The frequency of the capacitive sensing oscillator is equal to the number of counts on in the timer, divided by the period of the fixed time base. This frequency should be less than the value obtained during the nominal frequency measurement.
TABLE 26-2:
TMR1ON 0 0 1 1
TIMER1 ENABLE FUNCTION
TMR1GE 0 1 0 1 Timer1 Operation Off Off On Count Enabled by input
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26.7.3 FREQUENCY THRESHOLD
The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, "Software Handling for Capacitive Sensing" (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: * AN1101, "Introduction to Capacitive Sensing" (DS01101) * AN1102, "Layout and Physical Design Guidelines for Capacitive Sensing" (DS01102)
26.8
Operation during Sleep
The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake. However, the part does not have to be awake when the timer resource is acquiring counts. Note: Timer0 does not operate when in Sleep, and therefore, cannot be used for capacitive sense measurements in Sleep.
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REGISTER 26-1:
R/W-0/0 CPSON bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7 W = Writable bit x = Bit is unknown `0' = Bit is cleared CPSON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is enabled 0 = Capacitive sensing module is disabled CPSRM: Capacitive Sensing Reference Mode bit 1 = Capacitive sensing module is in high range. DAC and FVR provide oscillator voltage references. 0 = Capacitive sensing module is in the low range. Internal oscillator voltage references are used. Unimplemented: Read as `0' CPSRNG<1:0>: Capacitive Sensing Current Range bit If CPSRM = 0 (low range): 00 = Oscillator is off 01 = Oscillator is in Low Range. Charge/Discharge Current is nominally 0.1 A 10 = Oscillator is in Medium Range. Charge/Discharge Current is nominally 1.2 A 11 = Oscillator is in High Range. Charge/Discharge Current is nominally 18 A If CPSRM = 1 (high range): 00 = Oscillator is on. Noise Detection mode. No Charge/Discharge current is supplied. 01 = Oscillator is in Low Range. Charge/Discharge Current is nominally 9 A 10 = Oscillator is in Medium Range. Charge/Discharge Current is nominally 30 A 11 = Oscillator is in High Range. Charge/Discharge Current is nominally 100 A bit 1 CPSOUT: Capacitive Sensing Oscillator Status bit 1 = Oscillator is sourcing current (Current flowing out of the pin) 0 = Oscillator is sinking current (Current flowing into the pin) T0XCS: Timer0 External Clock Source Select bit If TMR0CS = 1: The T0XCS bit controls which clock external to the core/Timer0 module supplies Timer0: 1 = Timer0 clock source is the capacitive sensing oscillator 0 = Timer0 clock source is the T0CKI pin If TMR0CS = 0: Timer0 clock source is controlled by the core/Timer0 module and is FOSC/4 U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CPSCON0: CAPACITIVE SENSING CONTROL REGISTER 0
U-0 -- U-0 -- R/W-0/0 R/W-0/0 R-0/0 CPSOUT R/W-0/0 T0XCS bit 0 CPSRNG<1:0>
R/W-0/0 CPSRM
bit 6
bit 5-4 bit 3-2
bit 0
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REGISTER 26-2:
U-0 -- bit 7 Legend: R = Readable bit u = Bit is unchanged `1' = Bit is set bit 7-4 bit 3-0 W = Writable bit x = Bit is unknown `0' = Bit is cleared Unimplemented: Read as `0' CPSCH<3:0>: Capacitive Sensing Channel Select bits If CPSON = 0: These bits are ignored. No channel is selected. If CPSON = 1: 0000 = channel 0, (CPS0) 0001 = channel 1, (CPS1) 0010 = channel 2, (CPS2) 0011 = channel 3, (CPS3) 0100 = channel 4, (CPS4)(1) 0101 = channel 5, (CPS5)(1) 0110 = channel 6, (CPS6)(1) 0111 = channel 7, (CPS7)(1) 1000 = Reserved. Do not use. * * * 1111 = Reserved. Do not use. These channels are only implemented on the PIC16F/LF1823. PIC16F/LF1823 only. U = Unimplemented bit, read as `0' -n/n = Value at POR and BOR/Value at all other Resets
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
U-0 -- U-0 -- U-0 -- R/W-0/0(1) R/W-0/0 R/W-0/0 R/W-0/0 bit 0 CPSCH<3:2>(2) CPSCH<1:0>
Note 1: 2:
TABLE 26-3:
Name ANSELA ANSELC(1) CPSCON0 CPSCON1 INTCON OPTION_REG T1CON TRISA TRISC(1)
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
Bit 7 -- -- CPSON -- GIE WPUEN TMR1CS1 -- -- Bit 6 -- -- CPSRM -- PEIE INTEDG TMR1CS0 -- -- Bit 5 -- -- -- -- TMR0IE TMR0CS T1CKPS1 TRISA5 TRISC5 Bit 4 ANSA4 -- -- -- INTE TMR0SE T1CKPS0 TRISA4 TRISC4 Bit 3 -- ANSC3 Bit 2 ANSA2 ANSC2 Bit 1 ANSA1 ANSC1 CPSOUT CPSCH1 INTF PS1 -- TRISA1 TRISC1 Bit 0 ANSA0 ANSC0 T0XCS CPSCH0 IOCIF PS0 TMR1ON TRISA0 TRISC0 Register on Page 122 126 313 314 89 171 180 121 125
CPSRNG1 CPSRNG0 CPSCH3(1) CPSCH2(1) IOCIE PSA T1OSCEN TRISA3 TRISC3 TMR0IF PS2 T1SYNC TRISA2 TRISC2
Legend: -- = Unimplemented locations, read as `0'. Shaded cells are not used by the capacitive sensing module. Note 1: PIC16F/LF1823 only.
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PIC12F/LF1822/16F/LF1823
27.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM)
ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification" (DS41403).
27.1
High-Voltage Programming Entry Mode
The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 27-1 for example circuit.
FIGURE 27-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN VPP VDD VSS ICSP_DATA ICSP_CLOCK NC RJ11-6PIN (R) 1 2 3 4 5 6 6 5 4 3 2 1
To MPLAB ICD 2
R1 270 Ohm LM431BCMX 1 2A K 3 A U1 6A NC 4 7A NC 5 VREF 8
To Target Board
R2
R3
10k 1%
24k 1%
Note:
The ICD 2 produces a VPP voltage greater than the maximum VPP specification of the PIC12F/LF1822/16F/LF1823.
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PIC12F/LF1822/16F/LF1823
27.2 Low-Voltage Programming Entry Mode
FIGURE 27-2: ICD RJ-11 STYLE CONNECTOR INTERFACE
The Low-Voltage Programming Entry mode allows the PIC12F/LF1822/16F/LF1823 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.
VDD
ICSPDAT NC 246 ICSPCLK 13 5 VSS
VPP/MCLR
Target PC Board Bottom Side
Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect
Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 7.3 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode.
27.3
Common Programming Interfaces
Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 27-3.
Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6 connector) configuration. See Figure 27-2.
FIGURE 27-3:
PICkitTM STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description*
1 2 3 4 5 6
1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
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For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 27-4 for more information.
FIGURE 27-4:
TYPICAL CONNECTION FOR ICSPTM PROGRAMMING
External Programming Signals VDD VPP VSS Data Clock
VDD
Device to be Programmed VDD MCLR/VPP VSS ICSPDAT ICSPCLK
*
*
*
To Normal Connections
* Isolation devices (as required).
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NOTES:
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28.0 INSTRUCTION SET SUMMARY
28.1 Read-Modify-Write Operations
Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. * Byte Oriented * Bit Oriented * Literal and Control The literal and control category contains the most varied instruction word format. Table 28-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: * Subroutine takes two cycles (CALL, CALLW) * Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) * Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) * One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
TABLE 28-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. FSR or INDF number. (0-1) Pre-post increment-decrement mode selection
d
n mm
TABLE 28-2:
Field
PC TO C DC Z PD
ABBREVIATION DESCRIPTIONS
Description
Program Counter Time-out bit Carry bit Digit carry bit Zero bit Power-down bit
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FIGURE 28-1: GENERAL FORMAT FOR INSTRUCTIONS
0 Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 k (literal) 0 0
k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE
0
7
6 k (literal)
0
k = 7-bit immediate value MOVLB instruction only 13 OPCODE k = 5-bit immediate value BRA instruction only 13 OPCODE
54 k (literal)
0
9
8 k (literal)
0
k = 9-bit immediate value FSR Offset instructions 13 OPCODE
7
6 n
5 k (literal)
0
n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE n = appropriate FSR m = 2-bit mode value OPCODE only 13 OPCODE
3
21 0 n m (mode)
0
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TABLE 28-3:
Mnemonic, Operands
PIC12F/LF1822/16F/LF1823 ENHANCED INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f Decrement f, Skip if 0 Increment f, Skip if 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1(2) 1(2) 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1, 2 1, 2
BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ 1011 dfff ffff 1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF f, b f, b Bit Clear f Bit Set f 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2
BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW f, b f, b k k k k k k k k Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 1 (2) 1 (2) 1 1 1 1 1 1 1 1 01 01 11 11 11 00 11 11 11 11 10bb bfff ffff 11bb bfff ffff 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z 1, 2 1, 2
LITERAL OPERATIONS
C, DC, Z Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.
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TABLE 28-3:
Mnemonic, Operands
PIC12F/LF1822/16F/LF1823 ENHANCED INSTRUCTION SET (CONTINUED)
Description Cycles 14-Bit Opcode MSb 11 00 10 00 10 00 11 00 00 00 00 00 00 00 11 00 11 00 11 001k 0000 0kkk 0000 1kkk 0000 0100 0000 0000 0000 0000 0000 0000 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 0110 0000 0110 0000 0110 0110 LSb kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff Status Affected Notes
CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN CLRWDT NOP OPTION RESET SLEEP TRIS ADDFSR MOVIW k - k - k k k - - - - - - f n, k n k[n] n k[n] Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W Add Literal k to FSR, n = FSR0 or FSR1 Move indirect to W, n = FSR0 or FSR1, with pre/post inc/dec modifier. Move INDFn to W, Indexed Indirect. Move W to indirect, n = FSR0 or FSR1, with pre/post inc/dec modifier. Move W to INDFn, Indexed Indirect. 2 2 2 2 2 2 2 2 INHERENT OPERATIONS 1 1 1 1 1 1 1 1 1 1 1
C-COMPILER OPTIMIZED 0001 0nkk kkkk 0000 0001 0nmm Z Z 1111 0nkk kkkk 0000 0001 1nmm 1111 1nkk kkkk 2 2 2 2
MOVWI
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.
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28.2 Instruction Descriptions
Add Literal to FSRn
[ label ] ADDFSR FSRn, k -32 k 31 n [ 0, 1] FSR(n) + k FSR(n) None The signed 6-bit literal `k' is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around.
ADDFSR
Syntax: Operands: Operation: Status Affected: Description:
ANDLW
Syntax: Operands: Operation: Status Affected: Description:
AND literal with W
[ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
ANDWF ADDLW
Syntax: Operands: Operation: Status Affected: Description:
AND W with f
[ label ] ANDWF 0 f 127 d 0,1 (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
Add literal and W
[ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. k
Syntax: Operands: Operation: Status Affected: Description:
ASRF ADDWF
Syntax: Operands: Operation: Status Affected: Description:
Arithmetic Right Shift
[ label ] ASRF 0 f 127 d [0,1] (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. register f C f {,d}
Add W and f
[ label ] ADDWF 0 f 127 d 0,1 (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
Syntax: Operands: Operation:
Status Affected: Description:
ADDWFC
Syntax: Operands: Operation: Status Affected: Description:
ADD W and CARRY bit to f
[ label ] ADDWFC 0 f 127 d [0,1] (W) + (f) + (C) dest C, DC, Z Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. f {,d}
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BCF
Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f
[ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
BTFSC
Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear
[ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b', in register `f', is `0', the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction.
BRA
Syntax: Operands: Operation: Status Affected: Description:
Relative Branch
[ label ] BRA label [ label ] BRA $+k -256 label - PC + 1 255 -256 k 255 (PC) + 1 + k PC None Add the signed 9-bit literal `k' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a two-cycle instruction. This branch has a limited range.
BTFSS
Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set
[ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
BRW
Syntax: Operands: Operation: Status Affected: Description:
Relative Branch with W
[ label ] BRW None (PC) + (W) PC None Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a two-cycle instruction.
BSF
Syntax: Operands: Operation: Status Affected: Description:
Bit Set f
[ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
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CALL
Syntax: Operands: Operation:
Call Subroutine
[ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRWDT
Syntax: Operands: Operation:
Clear Watchdog Timer
[ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
CALLW
Syntax: Operands: Operation:
Subroutine Call With W
[ label ] CALLW None (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> None Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a two-cycle instruction.
COMF
Syntax: Operands: Operation: Status Affected: Description:
Complement f
[ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
Status Affected: Description:
CLRF
Syntax: Operands: Operation: Status Affected: Description:
Clear f
[ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
DECF
Syntax: Operands: Operation: Status Affected: Description:
Decrement f
[ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
CLRW
Syntax: Operands: Operation: Status Affected: Description:
Clear W
[ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
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DECFSZ
Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0
[ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2-cycle instruction.
INCFSZ
Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0
[ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2-cycle instruction.
GOTO
Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch
[ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
IORLW
Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W
[ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF
Syntax: Operands: Operation: Status Affected: Description:
Increment f
[ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF
Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f
[ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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LSLF
Syntax: Operands: Operation:
Logical Left Shift
[ label ] LSLF 0 f 127 d [0,1] (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> C, Z The contents of register `f' are shifted one bit to the left through the Carry flag. A `0' is shifted into the LSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. C register f 0 f {,d}
MOVF
Syntax: Operands: Operation: Status Affected: Description:
Move f
[ label ] MOVF f,d 0 f 127 d [0,1] (f) (dest) Z The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. 1 1 MOVF FSR, 0 After Instruction W = value in FSR register Z=1
Status Affected: Description:
Words: Cycles: Example:
LSRF
Syntax: Operands: Operation:
Logical Right Shift
[ label ] LSLF 0 f 127 d [0,1] 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, C, Z The contents of register `f' are shifted one bit to the right through the Carry flag. A `0' is shifted into the MSb. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. 0 register f C f {,d}
Status Affected: Description:
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MOVIW
Syntax:
Move INDFn to W
[ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] n [0,1] -32 k 31 If not present, k = 0. INDFn W Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) * Unchanged Z
MOVLP
Syntax: Operands: Operation: Status Affected: Description:
Move literal to PCLATH
[ label ] MOVLP k 0 k 127 k PCLATH None The seven-bit literal `k' is loaded into the PCLATH register.
Operands:
Operation:
MOVLW
Syntax: Operands: Operation: Status Affected: Description:
Move literal to W
[ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. 1 1 MOVLW 0x5A 0x5A After Instruction W= MOVLW k 0 k 255
Status Affected:
Words: Mode Preincrement Predecrement Postincrement Postdecrement Description: Syntax ++FSRn --FSRn FSRn++ FSRn-Cycles: Example:
MOVWF
Syntax: Operands: Operation: Status Affected: Description:
Move W to f
[ label ] (W) (f) None Move data from W register to register `f'. 1 1 MOVWF OPTION = = = = 0xFF 0x4F 0x4F 0x4F Before Instruction OPTION W After Instruction OPTION W MOVWF f 0 f 127
This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around.
Words: Cycles: Example:
MOVLB
Syntax: Operands: Operation: Status Affected: Description:
Move literal to BSR
[ label ] MOVLB k 0 k 15 k BSR None The five-bit literal `k' is loaded into the Bank Select Register (BSR).
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MOVWI
Syntax:
Move W to INDFn
[ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] n [0,1]. -32 k 31 If not present, k = 0. W INDFn Effective address is determined by * FSR + 1 (preincrement) * FSR - 1 (predecrement) * FSR + k (relative offset) After the Move, the FSR value will be either: * FSR + 1 (all increments) * FSR - 1 (all decrements) Unchanged None Mode Preincrement Predecrement Postincrement Postdecrement Syntax ++FSRn --FSRn FSRn++ FSRn--
NOP
Syntax: Operands: Operation: Status Affected: Description: Words: Cycles: Example:
No Operation
[ label ] None No operation None No operation. 1 1 NOP NOP
Operands:
Operation:
OPTION
Syntax: Operands: Operation: Status Affected: Description:
Load OPTION_REG Register with W
[ label ] OPTION None (W) OPTION_REG None Move data from W register to OPTION_REG register.
Status Affected:
RESET
Syntax: Operands: Operation: Status Affected: Description:
Software Reset
[ label ] RESET None Execute a device Reset. Resets the nRI flag of the PCON register. None This instruction provides a way to execute a hardware Reset by software.
Description:
This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h-FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits.
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RETFIE
Syntax: Operands: Operation: Status Affected: Description:
Return from Interrupt
[ label ] None TOS PC, 1 GIE None Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. 1 2 RETFIE After Interrupt PC = GIE = TOS 1 RETFIE k
RETURN
Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine
[ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
Words: Cycles: Example:
RETLW
Syntax: Operands: Operation: Status Affected: Description:
Return with literal in W
[ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. 1 2 CALL TABLE;W contains table ;offset value * ;W now has table value * * ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; * * * RETLW kn ; End of table Before Instruction W= After Instruction W=
RLF
Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry
[ label ] 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C Register f RLF f,d
Words: Cycles: Example:
Words: Cycles: Example:
1 1 RLF REG1,0 = = = = = 1110 0110 0 1110 0110 1100 1100 1 Before Instruction REG1 C After Instruction REG1 W C
TABLE
0x07 value of k8
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RRF
Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry
[ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C Register f
SUBLW
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from literal
[ label ] SUBLW k 0 k 255 k - (W) W) C, DC, Z The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
C=0 C=1 DC = 0 DC = 1
Wk Wk W<3:0> k<3:0> W<3:0> k<3:0>
SLEEP
Syntax: Operands: Operation:
Enter Sleep mode
[ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. SLEEP
SUBWF
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f
[ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) destination) C, DC, Z Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f.
Status Affected: Description:
C=0 C=1 DC = 0 DC = 1
Wf Wf W<3:0> f<3:0> W<3:0> f<3:0>
SUBWFB
Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f with Borrow
SUBWFB
0 f 127 d [0,1] (f) - (W) - (B) dest C, DC, Z Subtract W and the BORROW flag (CARRY) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'.
f {,d}
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SWAPF
Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f
[ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'.
XORLW
Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W
[ label ] XORLW k 0 k 255 (W) .XOR. k W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
TRIS
Syntax: Operands: Operation: Status Affected: Description:
Load TRIS Register with W
[ label ] TRIS f 5f7 (W) TRIS register `f' None Move data from W register to TRIS register. When `f' = 5, TRISA is loaded. When `f' = 6, TRISB is loaded. When `f' = 7, TRISC is loaded.
XORWF
Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f
[ label ] XORWF f,d 0 f 127 d [0,1] (W) .XOR. (f) destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
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29.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()
Ambient temperature under bias....................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS, PIC12F1822/16F1823 .............................................................. -0.3V to +6.5V Voltage on VDD with respect to VSS, PIC12LF1822/16LF1823 .......................................................... -0.3V to +4.0V Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) ............................................................................................................................... 800 mW Maximum current out of VSS pin, -40C TA +85C for industrial................................................................. 85 mA Maximum current out of VSS pin, -40C TA +125C for extended .............................................................. 35 mA Maximum current into VDD pin, -40C TA +85C for industrial.................................................................. 800 mA Maximum current into VDD pin, -40C TA +125C for extended ................................................................. 30 mA Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA Maximum output current sunk by any I/O pin.................................................................................................... 25 mA Maximum output current sourced by any I/O pin .............................................................................................. 25 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.
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FIGURE 29-1:
5.5
PIC12F1822/16F1823 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16 32
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies.
FIGURE 29-2:
PIC12LF1822/16LF1823 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
3.6 2.5 2.3 2.0 1.8 0 4 10 Frequency (MHz) 16 32
Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 29-1 for each Oscillator mode's supported frequencies.
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FIGURE 29-3:
125 5% 85 Temperature (C) 2.5% 60
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
25
2%
0 -20 -40 1.8 2.0 2.5 3.0 3.5 5% 4.0 VDD (V) 4.5 5.0 5.5
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PIC12F/LF1822/16F/LF1823
29.1 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC12LF1822/16LF1823 D001 D002* D002* VPOR* VPORR* VDR PIC12F1822/16F1823 RAM Data Retention Voltage(1) PIC12LF1822/16LF1823 PIC12F1822/16F1823 Power-on Reset Release Voltage Power-on Reset Rearm Voltage PIC12LF1822/16LF1823 PIC12F1822/16F1823 D003 VADFVR Fixed Voltage Reference Voltage for ADC, Initial Accuracy -- -- -5.5 -6.0 -5.5 -6.0 -5.5 -6.0 -5.5 -6.0 -5.5 -6.0 -5.5 -6.0 0.05 -- 0.8 1.7 -- -- 5.5 6 5.5 6 5.5 6 5.5 6 5.5 6 5.5 6 -- V V % Device in Sleep mode Device in Sleep mode 1.024V, VDD 2.5V, 85C 1.024V, VDD 2.5V, 125C 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C 1.024V, VDD 2.5V, 85C 1.024V, VDD 2.5V, 125C 2.048V, VDD 2.5V, 85C 2.048V, VDD 2.5V, 125C 4.096V, VDD 4.75V, 85C 4.096V, VDD 4.75V, 125C See Section 7.1 "Power-on Reset (POR)" for details. 1.5 1.7 -- -- -- 1.6 -- -- -- V V V Device in Sleep mode Device in Sleep mode 1.8 2.3 1.8 2.3 -- -- -- -- 3.6 3.6 5.5 5.5 V V V V FOSC 16 MHz: FOSC 32 MHz (NOTE 2) FOSC 16 MHz: FOSC 32 MHz (NOTE 2) Min. Typ Max. Units Conditions
PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param. No. D001 Sym. VDD
VCDAFVR
Fixed Voltage Reference Voltage for Comparator and DAC, Initial Accuracy
%
D004* * Note
SVDD
VDD Rise Rate to ensure internal Power-on Reset signal
V/ms
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation.
DS41413A-page 336
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
FIGURE 29-4:
VDD VPOR VPORR
POR AND POR REARM WITH SLOW RISING VDD
VSS NPOR
POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3)
When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 337
PIC12F/LF1822/16F/LF1823
29.2 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note
PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No. Device Characteristics Supply Current (IDD)(1, 2) D010 D010 -- -- -- -- -- D011 D011 -- -- -- -- -- D012 D012 -- -- -- -- -- D013 D013 -- -- -- -- -- D014 -- -- D014 -- -- -- * Note 1: 2:
8.0 12.0 23 28 33 60 110 82 141 200 145 260 165 290 368 34 59 60 92 126 118 210 143 240 300
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
A A A A A A A A A A A A A A A A A A A A A A A A A
1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 32 kHz LP Oscillator mode FOSC = 32 kHz LP Oscillator mode
FOSC = 1 MHz XT Oscillator mode FOSC = 1 MHz XT Oscillator mode
FOSC = 4 MHz XT Oscillator mode FOSC = 4 MHz XT Oscillator mode
FOSC = 1 MHz EC Oscillator mode, Medium-power mode FOSC = 1 MHz EC Oscillator mode Medium-power mode FOSC = 4 MHz EC Oscillator mode, Medium-power mode FOSC = 4 MHz EC Oscillator mode Medium-power mode
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
DS41413A-page 338
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
29.2 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No. Device Characteristics Supply Current (IDD)(1, 2) D015 D015 -- -- -- -- -- D016 D016 -- -- -- -- -- D017* D017* -- -- -- -- -- D018 D018 -- -- -- -- -- D019 D019 * Note 1: 2: -- -- -- --
2.0 4.0 18 24 25 110 150 150 210 270 .25 .45 .35 .55 .75 .47 .84 .7 1.0 1.4 1.6 1.8 1.6 1.8
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 3.0 3.6 3.0 5.0
FOSC = 31 kHz LFINTOSC mode FOSC = 31 kHz LFINTOSC mode
FOSC = 500 kHz MFINTOSC mode FOSC = 500 kHz MFINTOSC mode
FOSC = 8 MHz HFINTOSC mode FOSC = 8 MHz HFINTOSC mode
FOSC = 16 MHz HFINTOSC mode FOSC = 16 MHz HFINTOSC mode
FOSC = 32 MHz HFINTOSC mode (Note 3) FOSC = 32 MHz HFINTOSC mode (Note 3)
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 339
PIC12F/LF1822/16F/LF1823
29.2 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions VDD Note PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No. Device Characteristics Supply Current (IDD)(1, 2) D020 D020 D021 D021 -- -- -- -- -- -- -- -- -- * Note 1: 2:
1.3 1.6 3.3 3.8 300 500 350 550 620
-- -- -- -- -- -- -- -- --
mA mA mA mA A A A A A
3.0 3.6 3.0 5.0 1.8 3.0 1.8 3.0 5.0
FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 32 MHz HS Oscillator mode (Note 4) FOSC = 4 MHz EXTRC mode (Note 5) FOSC = 4 MHz EXTRC mode (Note 5)
3: 4: 5:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 8 MHz internal RC oscillator with 4x PLL enabled. 8 MHz crystal oscillator with 4x PLL enabled. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k.
DS41413A-page 340
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
29.3 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. (IPD)(2) -- -- D022 -- -- -- D023 D023 -- -- -- -- -- D023A D023A -- -- -- -- -- D024 D024 D025 D025 -- -- -- -- -- -- -- -- D026 D026 -- -- -- -- -- * Note 1: 0.02 0.03 14 14.5 15.5 0.3 0.75 14 17 18 8.5 8.5 32 38 68 8.0 30 33 0.6 1.8 3.0 3.5 4.0 0.1 0.1 15 20 24 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- A A A A A A A A A A A A A A mA A A A A A A A A A A A A A 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 3.0 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 A/D Current (Note 1, Note 3), no conversion in progress A/D Current (Note 1, Note 3), no conversion in progress T1OSC Current (Note 1) T1OSC Current (Note 1) BOR Current (Note 1) BOR Current (Note 1) FVR current (Note 1) FVR current (Note 1) LPWDT Current (Note 1) LPWDT Current (Note 1) WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive Typ Max. +85C Max. +125C Units Conditions VDD Note
PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No.
Device Characteristics Power-down Base Current
D022
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 341
PIC12F/LF1822/16F/LF1823
29.3 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min.
(2)
PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No.
Device Characteristics
Typ
Max. +85C
Max. +125C
Units
Conditions VDD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, one comparator enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) Comparator Current, Low Power mode, two comparators enabled (Note 1) Cap Sense High Power Oscillator mode (Note 1) Cap Sense High Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense Medium Power Oscillator mode (Note 1) Cap Sense Low Power Oscillator mode (Note 1) Cap Sense Low Power Oscillator mode (Note 1) Note A/D Current (Note 1, Note 3), conversion in progress A/D Current (Note 1, Note 3), conversion in progress
Power-down Base Current (IPD) D026A* D026A*
-- -- -- -- --
250 250 280 280 280 2.9 3.8 15 19 20 6.3 7.9 20 22 23 16 41 28 52 60 7.3 7.4 19 20 21 7.5 7.6 20 21 22
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
D027 D027
-- -- -- -- --
D027A D027A
-- -- -- -- --
D027B D027B
-- -- -- -- --
D028
-- --
D028
-- -- --
D028A
-- --
D028A
-- -- -- *
Note 1:
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC.
DS41413A-page 342
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
29.3 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min.
(2)
PIC12LF1822/16LF1823
PIC12F1822/16F1823 Param No.
Device Characteristics
Typ
Max. +85C
Max. +125C
Units
Conditions VDD 1.8 3.0 1.8 3.0 5.0 1.8 3.0 1.8 3.0 5.0 Note Comparator Current, High Power mode, one comparator enabled (Note 1) Comparator Current, High Power mode, one comparator enabled (Note 1) Comparator Current, High Power mode, two comparators enabled Comparator Current, High Power mode, two comparators enabled (Note 1)
Power-down Base Current (IPD) D028B
-- --
46 47 60 62 64 47 48 61 63 65
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- --
A A A A A A A A A A
D028B
-- -- --
D028C D028C
-- -- -- -- -- *
Note 1:
2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. A/D oscillator source is FRC.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 343
PIC12F/LF1822/16F/LF1823
29.4 DC Characteristics: PIC12F/LF1822/16F/LF1823-I/E
DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min. Typ Max. Units Conditions
Sym. VIL
Characteristic Input Low Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2CTM levels with SMBus levels
D030 D030A D031
-- -- -- -- -- -- --
-- -- -- -- -- -- -- --
0.8 0.15 VDD 0.2 VDD 0.3 VDD 0.8 0.2 VDD 0.3 VDD -- -- -- -- -- -- -- -- -- 125 1000 200 200 300
V V V V V V V
4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V
D032 D033 VIH D040 D040A D041
MCLR, OSC1 (RC mode)(1) OSC1 (HS mode) Input High Voltage I/O ports: with TTL buffer
2.0 0.25 VDD + 0.8
-- -- -- -- -- -- -- -- 5 5
V V V V V V V V nA nA nA
4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V
with Schmitt Trigger buffer with I2CTM levels with SMBus levels
0.8 VDD 0.7 VDD 2.1 0.8 VDD 0.7 VDD 0.9 VDD --
D042 D043A D043B IIL D060
MCLR OSC1 (HS mode) OSC1 (RC mode) Input Leakage Current(2) I/O ports
(Note 1) VSS VPIN VDD, Pin at highimpedance at 85C 125C VSS VPIN VDD at 85C VDD = 3.3V, VPIN = VSS VDD = 5.0V, VPIN = VSS IOL = 8mA, VDD = 5V IOL = 6mA, VDD = 3.3V IOL = 1.8mA, VDD = 1.8V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V In XT, HS and LP modes when external clock is used to drive OSC1
D061 IPUR D070* VOL D080
MCLR(3) Weak Pull-up Current
-- 25 25
50 100 140
A
Output Low Voltage(4) I/O ports -- -- 0.6 V
VOH D090
Output High Voltage(4) I/O ports VDD - 0.7 Capacitive Loading Specs on Output Pins -- -- V
D101*
COSC2 OSC2 pin
--
--
15
pF
D101A* CIO
All I/O pins
--
--
50
pF
*
Note 1: 2: 3: 4:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode.
DS41413A-page 344
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
29.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Characteristic Program Memory Programming Specifications D110 D111 D112
D113 VPEW
DC CHARACTERISTICS Param No. Sym.
Min.
Typ
Max.
Units
Conditions
VIHH IDDP
Voltage on MCLR/VPP/RA5 pin Supply Current during Programming
VDD for Bulk Erase VDD for Write or Row Erase
8.0 --
2.7 VDD min. -- --
-- --
-- -- --
9.0 10
VDD max. VDD max. 1.0 5.0
V mA
V V mA mA
(Note 3, Note 4)
D114 D115 D116 D117 D118 D119 D120
IPPPGM Current on MCLR/VPP during Erase/ Write IDDPGM Current on VDD during Erase/Write
Data EEPROM Memory ED VDRW TDEW Byte Endurance VDD for Read/Write Erase/Write Cycle Time 100K
VDD min.
--
--
--
VDD max.
E/W V ms Year E/W
-40C to +85C
-- 40 1M
4.0 -- 10M
5.0 -- --
TRETD Characteristic Retention TREF Number of Total Erase/Write Cycles before Refresh(2) Program Flash Memory Cell Endurance VDD for Read Self-timed Write Cycle Time
Provided no other specifications are violated -40C to +85C
D121 D122 D123 D124
EP VPR TIW
10K
VDD min.
--
--
--
VDD max.
E/W V ms Year
-40C to +85C (Note 1)
-- 40
2 --
2.5 --
TRETD Characteristic Retention
Provided no other specifications are violated
Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section 11.2 "Using the Data EEPROM" for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2.
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 345
PIC12F/LF1822/16F/LF1823
29.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. TH01 Sym. JA Characteristic Thermal Resistance Junction to Ambient Typ. TBD TBD TBD TBD TBD TBD TBD TH02 JC Thermal Resistance Junction to Case TBD TBD TBD TBD TBD TBD TBD TH03 TH04 TH05 TH06 TH07 TJMAX PD PI/O PDER Maximum Junction Temperature Power Dissipation I/O Power Dissipation Derated Power 150 -- -- -- -- Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C W W W W PD = PINTERNAL + PI/O PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER = PDMAX (TJ - TA)/JA(2) Conditions 8-pin PDIP package 8-pin SOIC package 8-pin DFN 3X3mm package 14-pin PDIP package 14-pin SOIC package 14-pin TSSOP 4x4mm package 16-pin QFN 4X4mm package 8-pin PDIP package 8-pin SOIC package 8-pin DFN 3X3mm package 14-pin PDIP package 14-pin SOIC package 14-pin TSSOP 4x4mm package 16-pin QFN 4X4mm package
PINTERNAL Internal Power Dissipation
Legend: TBD = To Be Determined Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature. 3: TJ = Junction Temperature.
DS41413A-page 346
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
29.7 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDIx do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low
T
Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCKx SS T0CKI T1CKI WR
P R V Z
Period Rise Valid High-impedance
FIGURE 29-5:
LOAD CONDITIONS
Load Condition
Pin
CL VSS
Legend: CL = 50 pF for all pins, 15 pF for OSC2 output
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 347
PIC12F/LF1822/16F/LF1823
29.8 AC Characteristics: PIC12F/LF1822/16F/LF1823-I/E
CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 29-6:
OSC1/CLKIN OS02 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OS04 OS04
OSC2/CLKOUT (CLKOUT Mode)
TABLE 29-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. DC DC DC Oscillator Frequency(1) -- 0.1 1 1 DC OS02 TOSC External CLKIN Period(1) 27 250 50 31.25 Oscillator Period(1) -- 250 50 250 OS03 OS04* TCY TosH, TosL TosR, TosF Instruction Cycle Time(1) External CLKIN High, External CLKIN Low External CLKIN Rise, External CLKIN Fall 125 2 100 20 OS05* 0 0 0 * Typ -- -- -- 32.768 -- -- -- -- -- -- -- -- 30.5 -- -- -- -- -- -- -- -- -- -- Max. 0.5 4 32 -- 4 4 20 4 -- 10,000 1,000 -- DC -- -- -- Units MHz MHz MHz kHz MHz MHz MHz MHz s ns ns ns s ns ns ns ns s ns ns ns ns ns Conditions EC Oscillator mode (low) EC Oscillator mode (medium) EC Oscillator mode (high) LP Oscillator mode XT Oscillator mode HS Oscillator mode, VDD 2.3V HS Oscillator mode, VDD > 2.3V RC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode EC Oscillator mode LP Oscillator mode XT Oscillator mode HS Oscillator mode RC Oscillator mode TCY = FOSC/4 LP oscillator XT oscillator HS oscillator LP oscillator XT oscillator HS oscillator
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
DS41413A-page 348
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 29-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS08 Sym. HFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Freq. Tolerance 2% 2.5% 5% OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) 2% 2.5% 5% OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time * -- Min. -- -- -- -- -- -- -- Typ 16.0 16.0 16.0 500 500 500 5 Max. -- -- -- -- -- -- 8 Units MHz MHz MHz kHz kHz kHz s Conditions 0C TA +60C, VDD 2.5V 60C TA +85C, VDD 2.5V -40C TA +125C 60C TA +60C, VDD 2.5V 0C TA +85C, VDD 2.5V -40C TA +125C
--
--
20
30
s
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 3: By design.
TABLE 29-3:
Param No. F10 F11 F12 F13* Sym.
PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
Characteristic Min. 4 16 -- -0.25% Typ -- -- -- -- Max. 8 32 2 +0.25% Units MHz MHz ms % Conditions
FOSC Oscillator Frequency Range FSYS TRC CLK On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter)
* These parameters are characterized but not tested. Data in "Typ" column is at 3V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 29-7:
Cycle
CLKOUT AND I/O TIMING
Write Q4 Fetch Q1 Read Q2 Execute Q3
FOSC OS11 CLKOUT OS19 OS13 I/O pin (Input) OS15 I/O pin (Output) Old Value OS18, OS19 OS14 New Value OS17 OS20 OS21 OS16 OS18 OS12
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TABLE 29-4: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. OS11 OS12 OS13 OS14 OS15 OS16 OS17 OS18 OS19 Sym. TosH2ckL TckL2ioV TioV2ckH TosH2ioV TosH2ioI TioV2osH TioR TioF Characteristic FOSC to CLKOUT (1)
(1) (1)
Min. -- -- -- TOSC + 200 ns -- 50 20 -- -- -- -- 25 25
Typ -- -- -- -- 50 -- -- 40 15 28 15 -- --
Max. 70 72 20 -- 70* -- -- 72 32 55 30 -- --
Units ns ns ns ns ns ns ns ns ns ns ns
Conditions VDD = 3.3-5.0V VDD = 3.3-5.0V
TosH2ckH FOSC to CLKOUT
CLKOUT to Port out valid
Port input valid before CLKOUT(1) Fosc (Q1 cycle) to Port out valid Fosc (Q2 cycle) to Port input invalid (I/O in hold time) Port input valid to Fosc(Q2 cycle) (I/O in setup time) Port output rise time(2) Port output fall time(2)
VDD = 3.3-5.0V VDD = 3.3-5.0V
VDD = 1.8V VDD = 3.3-5.0V VDD = 1.8V VDD = 3.3-5.0V
INT pin input high or low time Interrupt-on-change new input level time * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Includes OSC2 in CLKOUT mode.
OS20* Tinp OS21* Tioc
FIGURE 29-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 34 I/O pins Note 1: Asserted low. 31 34 33 32 30
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Preliminary
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FIGURE 29-9:
VDD VBOR VBOR and VHYST
BROWN-OUT RESET TIMING AND CHARACTERISTICS
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset (due to BOR)
33(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to `0'. 2 ms delay if PWRTE = 0 and VREGEN = 1.
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TABLE 29-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 30 31 32 33* 34* 35 36* 37* * Note 1: Sym. TMCL Characteristic MCLR Pulse Width (low) Min. 2 5 10 -- 40 -- 2.38 1.80 0 1 Typ -- -- 18 1024 65 -- 2.5 1.9 25 3 Max. -- -- 27 -- 140 2.0 2.65 2.05 50 5 Units s s ms Conditions VDD = 3.3-5V, -40C to +85C VDD = 3.3-5V VDD = 3.3V-5V
TWDTLP Low-Power Watchdog Timer Time-out Period (No Prescaler) TOST TPWRT TIOZ VBOR VHYST Oscillator Start-up Timer Period(1), (2) Power-up Timer Period, PWRTE = 0 I/O high-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Voltage Brown-out Reset Hysteresis
Tosc (Note 3) ms s V mV s BORV=2.5V BORV=1.9V -40C to +85C VDD VBOR
TBORDC Brown-out Reset DC Response Time
2: 3: 4:
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. By design. Period of the slower clock. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 29-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI 40 42 41
T1CKI 45 47 TMR0 or TMR1 46 49
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TABLE 29-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. 40* 41* 42* Sym. TT0H TT0L TT0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 32.4 2 TOSC Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (2, 4, ..., 256) Conditions
45*
TT1H
T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Time Synchronous, No Prescaler Synchronous, with Prescaler Asynchronous
-- -- -- -- -- -- --
-- -- -- -- -- -- --
ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46*
TT1L
47*
TT1P
T1CKI Input Synchronous Period Asynchronous
-- 32.768 --
-- 33.1 7 TOSC
ns kHz -- Timers in Sync mode
48 49* *
FT1
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZTMR1 Delay from External Clock Edge to Timer Increment
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-11:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP (Capture mode)
CC01 CC03 Note: Refer to Figure 29-5 for load conditions.
CC02
TABLE 29-7:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * Characteristic CCP Input Low Time CCP Input High Time CCP Input Period No Prescaler With Prescaler No Prescaler With Prescaler Min. 0.5TCY + 20 20 0.5TCY + 20 20 3TCY + 40 N Typ -- -- -- -- -- Max. -- -- -- -- -- Units ns ns ns ns ns N = prescale value (1, 4 or 16) Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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TABLE 29-8: PIC12F/LF1822/16F/LF1823 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 * Note 1: 2: 3: 4: NR EIL EDL Characteristic Resolution Integral Error Differential Error Min. -- -- -- -- -- 1.8 VSS -- Typ -- -- -- -- -- -- -- -- Max. 10 1.7 1 2 1.5 VDD VREF 50 Units bit LSb VREF = 3.0V LSb No missing codes VREF = 3.0V LSb VREF = 3.0V LSb VREF = 3.0V V V Conditions
EOFF Offset Error EGN VAIN ZAIN Gain Error Full-Scale Range Recommended Impedance of Analog Voltage Source VREF Reference Voltage(3)
k Can go higher if external 0.01F capacitor is
present on input pin.
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Total Absolute Error includes integral, differential, offset and gain errors. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input. When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module.
TABLE 29-9:
PIC12F/LF1822/16F/LF1823 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param No. Sym. Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Acquisition Time Min. 1.0 1.0 -- -- Typ -- 1.6 11 5.0 Max. 9.0 6.0 -- -- Units s s TAD s TOSC-based ADCS<1:0> = 11 (ADRC mode) Set GO/DONE bit to conversion complete Conditions
AD130* TAD
AD132* TACQ *
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle.
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Preliminary
DS41413A-page 355
PIC12F/LF1822/16F/LF1823
FIGURE 29-12: PIC12F/LF1822/16F/LF1823 A/D CONVERSION TIMING (NORMAL MODE)
1 TCY AD131 AD130 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 OLD_DATA 5 4 3 2 1 0 NEW_DATA 1 TCY DONE BSF ADCON0, GO AD134 Q4
(TOSC/2(1))
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
FIGURE 29-13:
PIC12F/LF1822/16F/LF1823 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO AD134 Q4 A/D CLK A/D Data ADRES ADIF GO Sample AD132 Sampling Stopped 7 6 5 4 3 2 1 0 NEW_DATA 1 TCY DONE (TOSC/2 + TCY(1)) AD131 AD130 1 TCY
OLD_DATA
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC12F/LF1822/16F/LF1823
TABLE 29-10: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. CM01 CM02 CM03 CM04 CM05 CM06 * Note 1: Sym. VIOFF VICM CMRR TRESP TMC2OV Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time Comparator Mode Change to Output Valid* Min. -- 0 -- -- -- -- Typ. 7.5 -- 50 150 -- 65 Max. 60 VDD -- 400 10 -- Units mV V dB ns s mV Note 1 Comments
CHYSTER Comparator Hysteresis
These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
TABLE 29-11: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. DAC01* DAC02* DAC03* DAC04* Sym. CLSB CACC CR CST Characteristics Step Size(2) Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min. -- -- -- -- Typ. VDD/32 -- TBD -- Max. -- 1/2 -- 10 Units V LSb s Comments
* These parameters are characterized but not tested. Legend: TBD = To Be Determined Note 1: Settling time measured while DACR<4:0> transitions from `0000' to `1111'.
TABLE 29-12: PIC12F/LF1822/16F/LF1823 LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +125C Param Sym. No. LD001 LD002 * Characteristic LDO Regulation Voltage LDO External Capacitor Min. -- 0.1 Typ 3.2 -- Max. -- 1 Units V F Conditions
These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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Preliminary
DS41413A-page 357
PIC12F/LF1822/16F/LF1823
FIGURE 29-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK US121 DT US120 Note: Refer to Figure 29-5 for load conditions. US122 US121
TABLE 29-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V Min. -- -- -- -- -- -- Max. 80 100 45 50 45 50 Units ns ns ns ns ns ns Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid US121 TCKRF US122 TDTRF Clock out rise time and fall time (Master mode) Data-out rise time and fall time
FIGURE 29-15:
CK DT
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
US125
US126 Note: Refer to Figure 29-5 for load conditions.
TABLE 29-14: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param. No. Symbol Characteristic Min. 10 15 Max. -- -- Units ns ns Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL Data-hold after CK (DT hold time)
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PIC12F/LF1822/16F/LF1823
FIGURE 29-16:
SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SCKx (CKP = 1) SP79 SP80 SDOx MSb bit 6 - - - - - -1 SP75, SP76 SDIx MSb In SP74 SP73 Note: Refer to Figure 29-5 for load conditions. bit 6 - - - -1 LSb In LSb SP78 SP79
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
FIGURE 29-17:
SSx
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SP81 SCKx (CKP = 0) SP71 SP73 SCKx (CKP = 1) SP80 SP78 LSb SP72 SP79
SDOx
MSb
bit 6 - - - - - -1 SP75, SP76
SDIx
MSb In SP74
bit 6 - - - -1
LSb In
Note: Refer to Figure 29-5 for load conditions.
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Preliminary
DS41413A-page 359
PIC12F/LF1822/16F/LF1823
FIGURE 29-18:
SSx SP70 SCKx (CKP = 0) SP71 SP72 SP78 SCKx (CKP = 1) SP79 SP80 SDOx MSb bit 6 - - - - - -1 SP75, SP76 SDIx MSb In SP74 SP73 Note: Refer to Figure 29-5 for load conditions. bit 6 - - - -1 LSb In LSb SP77 SP78 SP79 SP83
SPI SLAVE MODE TIMING (CKE = 0)
FIGURE 29-19:
SSx
SPI SLAVE MODE TIMING (CKE = 1)
SP82 SP70
SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP80 SP72
SP83
SDOx
MSb
bit 6 - - - - - -1 SP75, SP76
LSb SP77
SDIx
MSb In SP74
bit 6 - - - -1
LSb In
Note: Refer to Figure 29-5 for load conditions.
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2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
TABLE 29-15: SPI MODE REQUIREMENTS
Param No. Symbol Characteristic Min. TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- Tcy -- 1.5TCY + 40 3.0-5.5V 1.8-5.5V 3.0-5.5V 1.8-5.5V Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max. Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SP70* TSSL2SCH, SSx to SCKx or SCKx input TSSL2SCL SP71* TSCH SP72* TSCL SCKx input high time (Slave mode) SCKx input low time (Slave mode)
SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR SP76* TDOF SP77* TSSH2DOZ SP78* TSCR SP79* TSCF Hold time of SDIx data input to SCKx edge SDO data output rise time SDOx data output fall time SSx to SDOx output high-impedance SCKx output rise time (Master mode) 3.0-5.5V 1.8-5.5V
SCKx output fall time (Master mode)
SP80* TSCH2DOV, SDOx data output valid after TSCL2DOV SCKx edge
SP81* TDOV2SCH, SDOx data output setup to SCKx edge TDOV2SCL SP82* TSSL2DOV SDOx data output valid after SS edge SP83* TSCH2SSH, SSx after SCKx edge TSCL2SSH
* These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-20:
I2CTM BUS START/STOP BITS TIMING
SCLx SP91 SP90 SDAx SP92 SP93
Start Condition Note: Refer to Figure 29-5 for load conditions.
Stop Condition
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Preliminary
DS41413A-page 361
PIC12F/LF1822/16F/LF1823
FIGURE 29-21: I2CTM BUS DATA TIMING
SP103 SCLx SP100 SP101 SP102
SP90 SP91
SP106
SP107
SP92 SP110
SDAx In SP109 SDAx Out Note: Refer to Figure 29-5 for load conditions. SP109
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PIC12F/LF1822/16F/LF1823
TABLE 29-16: I2CTM BUS DATA REQUIREMENTS
Param. No. Symbol Characteristic Clock high time 100 kHz mode 400 kHz mode SSPx module SP101* TLOW Clock low time 100 kHz mode 400 kHz mode SSPx module SP102* TR SDAx and SCLx rise time 100 kHz mode 400 kHz mode Min. 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 0 0 250 100 -- -- 4.7 1.3 -- Max. -- -- -- -- -- -- 1000 300 250 250 -- 0.9 -- -- 3500 -- -- -- 400 Units s s -- s s -- ns ns ns ns ns s ns ns ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
SP100* THIGH
SP103* TF
SDAx and SCLx fall 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
SP106* THD:DAT SP107* TSU:DAT SP109* TAA SP110* TBUF
SP111 * Note 1: 2:
CB
Bus capacitive loading
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2CTM bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx signal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCLx line is released.
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Preliminary
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TABLE 29-17: CAP SENSE OSCILLATOR SPECIFICATIONS
Param. No. CS01 Symbol ISRC Characteristic Current Source High Medium Low CS02 ISNK Current Sink High Medium Low CS03 CS04 CS05 VCTH VCTL Cap Threshold Cap Threshold High Medium Low Min. -3 -0.8 -0.1 2.5 0.6 0.1 -- -- 350 250 175 Typ -8 -1.5 -0.3 7.5 1.5 0.25 0.8 0.4 525 375 300 Max. -15 -3 -0.4 14 2.9 0.6 -- -- 725 500 425 Units A A A A A A mV mV mV mV mV Conditions
VCHYST CAP HYSTERESIS (VCTH - VCTL)
* These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 29-22:
CAP SENSE OSCILLATOR
VCTH
VCTL
ISRC Enabled
ISNK Enabled
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30.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
Graphs and charts are not available at this time.
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Preliminary
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NOTES:
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PIC12F/LF1822/16F/LF1823
31.0 DEVELOPMENT SUPPORT
31.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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Preliminary
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PIC12F/LF1822/16F/LF1823
31.2 MPASM Assembler 31.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
31.6
MPLAB SIM Software Simulator
31.3
MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
31.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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31.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 31.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
31.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
31.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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31.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
31.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
31.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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32.0
32.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP Example
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12F1822/P 017 0910
Example PIC12F1822 /SN0910 017
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Example
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In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
*
Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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32.2 Package Marking Information
14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (.150") XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16F1823-I/P 0910017
Example PIC16F1823 -I/SL 0910017
14-Lead TSSOP
Example
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1823/ST 0910 017
16-Lead QFN (4x4x0.9 mm)
Example
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16F1823 -I/ML 0910017
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e3
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*
Standard PICmicro(R) device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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32.3 Package Details
The following sections give the technical details of the packages.
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Note:
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NOTES:
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APPENDIX A:
Revision A
Original release (03/2010)
DATA SHEET REVISION HISTORY
APPENDIX B:
MIGRATING FROM OTHER PIC(R) DEVICES
This section provides comparisons when migrating devices to the from other similar PIC(R) PIC12F/LF1822/16F/LF1823 family of devices.
B.1
PIC16F648A to PIC16F/LF1823
FEATURE COMPARISON
PIC16F648A PIC16F/LF1823 20 MHz 4K 256 256 10-bit 2/1 Y RB<7:0> RB<7:4> 2 1/0 N N 48 kHz or 4 MHz Y N 2/0 N 0 N N N N Y 32 MHz 4K 384 256 10-bit 4/1 Y RA<5:0>, RA2 RA<5:0>, Edge Selectable 2 0/2 Y Y 31 kHz 32 MHz Y Y 2/2 Y 2/0 Y Y Y Y Y Feature
TABLE B-1:
Max. Operating Speed Max. Program Memory (Words)
Max. SRAM (Bytes) Max. EEPROM (Bytes) A/D Resolution Timers (8/16-bit) Brown-out Reset Internal Pull-ups Interrupt-on-change Comparator AUSART/EUSART Extended WDT Software Control Option of WDT/BOR INTOSC Frequencies Clock Switching Capacitive Sensing CCP/ECCP Enhanced PIC16 CPU MSSPx/SSPx Reference Clock Data Signal Modulator SR Latch Voltage Reference DAC
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INDEX
A
A/D Specifications............................................................ 355 Absolute Maximum Ratings .............................................. 333 AC Characteristics Industrial and Extended ............................................ 348 Load Conditions ........................................................ 347 ACKSTAT ......................................................................... 261 ACKSTAT Status Flag ...................................................... 261 ADC .................................................................................. 133 Acquisition Requirements ......................................... 143 Associated registers.................................................. 145 Block Diagram........................................................... 133 Calculating Acquisition Time..................................... 143 Channel Selection..................................................... 134 Configuration............................................................. 134 Configuring Interrupt ................................................. 138 Conversion Clock...................................................... 134 Conversion Procedure .............................................. 138 Internal Sampling Switch (RSS) Impedance.............. 143 Interrupts................................................................... 136 Operation .................................................................. 137 Operation During Sleep ............................................ 137 Port Configuration ..................................................... 134 Reference Voltage (VREF)......................................... 134 Source Impedance.................................................... 143 Special Event Trigger................................................ 137 Starting an A/D Conversion ...................................... 136 ADCON0 Register....................................................... 32, 139 ADCON1 Register....................................................... 32, 140 ADDFSR ........................................................................... 323 ADDWFC .......................................................................... 323 ADRESH Register............................................................... 32 ADRESH Register (ADFM = 0) ......................................... 141 ADRESH Register (ADFM = 1) ......................................... 142 ADRESL Register (ADFM = 0).......................................... 141 ADRESL Register (ADFM = 1).......................................... 142 Alternate Pin Function....................................................... 117 Analog-to-Digital Converter. See ADC ANSELA Register ............................................................. 122 ANSELC Register ............................................................. 126 APFCON0 Register........................................................... 118 Assembler MPASM Assembler................................................... 368 EUSART Transmit .................................................... 279 External RC Mode ...................................................... 58 Fail-Safe Clock Monitor (FSCM)................................. 66 Generic I/O Port........................................................ 117 Interrupt Logic............................................................. 83 On-Chip Reset Circuit................................................. 75 Peripheral Interrupt Logic ........................................... 84 PIC16F/LF1826/27 ..................................................... 12 PIC16F193X/LF193X ................................................. 20 PWM (Enhanced) ..................................................... 208 Resonator Operation .................................................. 57 Timer0 ...................................................................... 169 Timer1 ...................................................................... 172 Timer1 Gate.............................................. 177, 178, 179 Timer2 ...................................................................... 184 Voltage Reference.................................................... 131 Voltage Reference Output Buffer Example .............. 150 BORCON Register.............................................................. 77 BRA .................................................................................. 324 Break Character (12-bit) Transmit and Receive ............... 299 Brown-out Reset (BOR)...................................................... 77 Specifications ........................................................... 353 Timing and Characteristics ....................................... 352
C
C Compilers MPLAB C18.............................................................. 368 MPLAB C30.............................................................. 368 CALL................................................................................. 325 CALLW ............................................................................. 325 Capacitive Sensing ........................................................... 307 Associated registers w/ Capacitive Sensing............. 314 Specifications ........................................................... 364 Capture Module. See Enhanced Capture/Compare/ PWM (ECCP) Capture/Compare/PWM ................................................... 199 Capture/Compare/PWM (CCP) Associated Registers w/ Capture ............................. 201 Associated Registers w/ Compare ........................... 203 Associated Registers w/ PWM ......................... 207, 220 Capture Mode........................................................... 200 CCPx Pin Configuration............................................ 200 Compare Mode......................................................... 202 CCPx Pin Configuration.................................... 202 Software Interrupt Mode ........................... 200, 202 Special Event Trigger ....................................... 202 Timer1 Mode Resource ............................ 200, 202 Prescaler .................................................................. 200 PWM Mode Duty Cycle ........................................................ 205 Effects of Reset ................................................ 207 Example PWM Frequencies and Resolutions, 20 MHZ ................................ 206 Example PWM Frequencies and Resolutions, 32 MHZ ................................ 206 Example PWM Frequencies and Resolutions, 8 MHz .................................. 206 Operation in Sleep Mode.................................. 207 Resolution ........................................................ 206 System Clock Frequency Changes .................. 207 PWM Operation ........................................................ 204 PWM Overview......................................................... 204 PWM Period ............................................................. 205 PWM Setup .............................................................. 205
B
BAUDCON Register.......................................................... 290 BF ............................................................................. 261, 263 BF Status Flag .......................................................... 261, 263 Block Diagram Capacitive Sensing ........................................... 307, 308 Block Diagrams (CCP) Capture Mode Operation ............................... 200 ADC .......................................................................... 133 ADC Transfer Function ............................................. 144 Analog Input Model ........................................... 144, 164 CCP PWM................................................................. 204 Clock Source............................................................... 55 Comparator ............................................................... 160 Compare ................................................................... 202 Crystal Operation .................................................. 57, 58 Digital-to-Analog Converter (DAC)............................ 149 EUSART Receive ..................................................... 280
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CCP1AS Register ............................................................. 222 CCP1CON Register ............................................................ 36 CCPR1H Register ............................................................... 36 CCPR1L Register................................................................ 36 CCPxCON (ECCPx) Register ........................................... 221 CLKRCON Register ............................................................ 72 Clock Accuracy with Asynchronous Operation ................. 288 Clock Sources External Modes ........................................................... 56 EC ....................................................................... 56 HS ....................................................................... 56 LP........................................................................ 56 OST..................................................................... 57 RC....................................................................... 58 XT ....................................................................... 56 Internal Modes ............................................................ 59 HFINTOSC.......................................................... 59 Internal Oscillator Clock Switch Timing............... 61 LFINTOSC .......................................................... 60 MFINTOSC ......................................................... 59 Clock Switching................................................................... 63 CMOUT Register............................................................... 166 CMxCON0 Register .......................................................... 165 CMxCON1 Register .......................................................... 166 Code Examples A/D Conversion ......................................................... 138 Changing Between Capture Prescalers .................... 200 Initializing PORTA ..................................................... 119 Initializing PORTC..................................................... 124 Write Verify ............................................................... 113 Writing to Flash Program Memory ............................ 111 Comparator Associated Registers ................................................ 167 Operation .................................................................. 159 Comparator Module .......................................................... 159 Cx Output State Versus Input Conditions ................. 162 Comparator Specifications ................................................ 357 Comparators C2OUT as T1 Gate ................................................... 174 Compare Module. See Enhanced Capture/ Compare/PWM (ECCP) CONFIG1 Register.............................................................. 50 CONFIG2 Register.............................................................. 52 CPSCON0 Register .......................................................... 313 CPSCON1 Register .......................................................... 314 Customer Change Notification Service ............................. 395 Customer Notification Service........................................... 395 Customer Support ............................................................. 395 Code Protection .......................................................... 53 Configuration Word..................................................... 49 User ID ................................................................. 53, 54 Device Overview........................................................... 11, 99 Digital-to-Analog Converter (DAC) ................................... 147 Associated Registers ................................................ 152 Effects of a Reset ..................................................... 149 Specifications ........................................................... 357
E
ECCP/CCP. See Enhanced Capture/Compare/PWM EEADR Registers ............................................................. 103 EEADRH Registers........................................................... 103 EEADRL Register ............................................................. 114 EEADRL Registers ........................................................... 103 EECON1 Register..................................................... 103, 115 EECON2 Register..................................................... 103, 116 EEDATH Register............................................................. 114 EEDATL Register ............................................................. 114 EEPROM Data Memory Avoiding Spurious Write ........................................... 104 Write Verify ............................................................... 113 Effects of Reset PWM mode ............................................................... 207 Electrical Specifications .................................................... 333 Enhanced Capture/Compare/PWM (ECCP)..................... 200 Enhanced PWM Mode.............................................. 208 Auto-Restart ..................................................... 216 Auto-shutdown.................................................. 215 Direction Change in Full-Bridge Output Mode.. 214 Full-Bridge Application...................................... 212 Full-Bridge Mode .............................................. 212 Half-Bridge Application ..................................... 211 Half-Bridge Application Examples .................... 217 Half-Bridge Mode.............................................. 211 Output Relationships (Active-High and Active-Low)............................................... 209 Output Relationships Diagram.......................... 210 Programmable Dead Band Delay..................... 217 Shoot-through Current ...................................... 217 Start-up Considerations .................................... 219 Specifications ........................................................... 354 Enhanced Mid-range CPU.................................................. 19 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .............................. 279 Errata .................................................................................. 10 EUSART ........................................................................... 279 Associated Registers Baud Rate Generator ....................................... 292 Asynchronous Mode ................................................. 281 12-bit Break Transmit and Receive .................. 299 Associated Registers Receive .................................................... 287 Transmit.................................................... 283 Auto-Wake-up on Break ................................... 297 Baud Rate Generator (BRG) ............................ 291 Clock Accuracy................................................. 288 Receiver ........................................................... 284 Setting up 9-bit Mode with Address Detect ...... 286 Transmitter ....................................................... 281 Baud Rate Generator (BRG) Auto Baud Rate Detect..................................... 296 Baud Rate Error, Calculating............................ 291 Baud Rates, Asynchronous Modes .................. 293 Formulas........................................................... 292 High Baud Rate Select (BRGH Bit) .................. 291
D
DACCON0 (Digital-to-Analog Converter Control 0) Register.................................................................... 151 DACCON1 (Digital-to-Analog Converter Control 1) Register.................................................................... 151 Data EEPROM Memory .................................................... 103 Associated Registers ................................................ 116 Code Protection ........................................................ 104 Reading..................................................................... 104 Writing ....................................................................... 104 Data Memory....................................................................... 23 DC and AC Characteristics ............................................... 365 DC Characteristics Extended and Industrial ............................................ 344 Industrial and Extended ............................................ 336 Development Support ....................................................... 367 Device Configuration........................................................... 49
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Synchronous Master Mode ............................... 300, 304 Associated Registers Receive..................................................... 303 Transmit.................................................... 301 Reception.......................................................... 302 Transmission .................................................... 300 Synchronous Slave Mode Associated Registers Receive..................................................... 305 Transmit.................................................... 304 Reception.......................................................... 305 Transmission .................................................... 304 Extended Instruction Set ADDFSR ................................................................... 323 MOVF ....................................................................... 327 MOVIW ..................................................................... 328 MOVLB ..................................................................... 328 MOVWI ..................................................................... 329 OPTION.................................................................... 329 RESET...................................................................... 329 SUBWFB .................................................................. 331 TRIS ......................................................................... 332 BCF .......................................................................... 324 BSF........................................................................... 324 BTFSC...................................................................... 324 BTFSS ...................................................................... 324 CALL......................................................................... 325 CLRF ........................................................................ 325 CLRW ....................................................................... 325 CLRWDT .................................................................. 325 COMF ....................................................................... 325 DECF........................................................................ 325 DECFSZ ................................................................... 326 GOTO ....................................................................... 326 INCF ......................................................................... 326 INCFSZ..................................................................... 326 IORLW ...................................................................... 326 IORWF...................................................................... 326 MOVLW .................................................................... 328 MOVWF.................................................................... 328 NOP.......................................................................... 329 RETFIE..................................................................... 330 RETLW ..................................................................... 330 RETURN................................................................... 330 RLF........................................................................... 330 RRF .......................................................................... 331 SLEEP ...................................................................... 331 SUBLW..................................................................... 331 SUBWF..................................................................... 331 SWAPF..................................................................... 332 XORLW .................................................................... 332 XORWF .................................................................... 332 INTCON Register................................................................ 89 Internal Oscillator Block INTOSC Specifications ................................................... 349 Internal Sampling Switch (RSS) Impedance ..................... 143 Internet Address ............................................................... 395 Interrupt-On-Change......................................................... 127 Associated Registers................................................ 129 Interrupts ............................................................................ 83 ADC .......................................................................... 138 Associated registers w/ Interrupts .............................. 94 Configuration Word w/ Clock Sources........................ 70 Configuration Word w/ Reference Clock Sources ...... 73 TMR1........................................................................ 176 INTOSC Specifications ..................................................... 349 IOCAF Register ................................................................ 128 IOCAN Register ................................................................ 128 IOCAP Register ................................................................ 128
F
Fail-Safe Clock Monitor....................................................... 66 Fail-Safe Condition Clearing ....................................... 66 Fail-Safe Detection ..................................................... 66 Fail-Safe Operation..................................................... 66 Reset or Wake-up from Sleep..................................... 66 Firmware Instructions........................................................ 319 Fixed Voltage Reference (FVR) ........................................ 131 Associated Registers ................................................ 132 Flash Program Memory .................................................... 103 Erasing...................................................................... 108 Modifying................................................................... 112 Writing....................................................................... 108 FSR Register .......... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 FVRCON (Fixed Voltage Reference Control) Register ..... 132
I
I2C Mode (MSSPx) Acknowledge Sequence Timing................................ 265 Bus Collision During a Repeated Start Condition ................... 270 During a Stop Condition.................................... 271 Effects of a Reset...................................................... 266 I2C Clock Rate w/BRG.............................................. 273 Master Mode Operation .......................................................... 257 Reception.......................................................... 263 Start Condition Timing .............................. 259, 260 Transmission .................................................... 261 Multi-Master Communication, Bus Collision and Arbitration .................................................. 266 Multi-Master Mode .................................................... 266 Read/Write Bit Information (R/W Bit) ........................ 242 Slave Mode Transmission .................................................... 247 Sleep Operation ........................................................ 266 Stop Condition Timing............................................... 265 INDF Register ......... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 Indirect Addressing ............................................................. 45 Instruction Format ............................................................. 320 Instruction Set ................................................................... 319 ADDLW ..................................................................... 323 ADDWF..................................................................... 323 ADDWFC .................................................................. 323 ANDLW ..................................................................... 323 ANDWF..................................................................... 323 BRA........................................................................... 324 CALL ......................................................................... 325 CALLW...................................................................... 325 LSLF ......................................................................... 327 LSRF......................................................................... 327
L
LATA Register .......................................................... 122, 125 Load Conditions................................................................ 347 LSLF ................................................................................. 327 LSRF ................................................................................ 327
M
Master Synchronous Serial Port. See MSSPx MCLR ................................................................................. 78
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Internal ........................................................................ 78 MDCARH Register ............................................................ 196 MDCARL Register............................................................. 197 MDCON Register .............................................................. 194 MDSRC Register............................................................... 195 Memory Organization.......................................................... 21 Data ............................................................................ 23 Program ...................................................................... 21 Microchip Internet Web Site .............................................. 395 Migrating from other PIC Microcontroller Devices............. 387 MOVIW.............................................................................. 328 MOVLB.............................................................................. 328 MOVWI.............................................................................. 329 MPLAB ASM30 Assembler, Linker, Librarian ................... 368 MPLAB ICD 2 In-Circuit Debugger.................................... 369 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 369 MPLAB Integrated Development Environment Software .. 367 MPLAB PM3 Device Programmer..................................... 369 MPLAB REAL ICE In-Circuit Emulator System................. 369 MPLINK Object Linker/MPLIB Object Librarian ................ 368 MSSPx .............................................................................. 225 I2C Mode Operation .................................................. 238 SPI Mode .................................................................. 228 SSPxBUF Register ................................................... 232 SSPxSR Register...................................................... 232 PIR1 Register ............................................................... 31, 92 PIR2 Register ......................................................... 31, 32, 93 PORTA ............................................................................. 119 ANSELA Register ..................................................... 119 Associated Registers ................................................ 123 Configuration Word w/ PORTA................................. 123 LATA Register ............................................................ 33 PORTA Register ......................................................... 31 Specifications ........................................................... 351 PORTA Register ............................................................... 121 PORTC ............................................................................. 124 ANSELC Register ..................................................... 124 Associated Registers ................................................ 126 LATC Register ............................................................ 33 Pin Descriptions and Diagrams ................................ 124 PORTC Register......................................................... 31 PORTC Register............................................................... 125 Power-Down Mode (Sleep)................................................. 95 Associated Registers .......................................... 97, 197 Power-on Reset .................................................................. 76 Power-up Time-out Sequence ............................................ 78 Power-up Timer (PWRT) .................................................... 76 Specifications ........................................................... 353 PR2 Register ...................................................................... 31 Precision Internal Oscillator Parameters .......................... 349 Program Memory ................................................................ 21 Map and Stack (PIC16F/LF1826) ............................... 22 Map and Stack (PIC16F/LF1826/27) .................... 21, 22 Programming, Device Instructions .................................... 319 PSTRxCON Register ........................................................ 224 PWM (ECCP Module) PWM Steering........................................................... 218 Steering Synchronization.......................................... 219 PWM Mode. See Enhanced Capture/Compare/PWM ...... 208 PWM Steering................................................................... 218 PWM1CON Register......................................................... 223
O
OPCODE Field Descriptions ............................................. 319 OPTION ............................................................................ 329 OPTION Register .............................................................. 171 OSCCON Register .............................................................. 68 Oscillator Associated Registers .................................................. 70 Oscillator Module ................................................................ 55 EC ............................................................................... 55 HS ............................................................................... 55 INTOSC ...................................................................... 55 LP................................................................................ 55 RC ............................................................................... 55 XT ............................................................................... 55 Oscillator Parameters........................................................ 349 Oscillator Specifications .................................................... 348 Oscillator Start-up Timer (OST) Specifications ............................................................ 353 Oscillator Switching Fail-Safe Clock Monitor............................................... 66 Two-Speed Clock Start-up .......................................... 64 OSCSTAT Register............................................................. 69 OSCTUNE Register ............................................................ 70
R
RCREG............................................................................. 286 RCREG Register ................................................................ 34 RCSTA Register ......................................................... 34, 289 Reader Response............................................................. 396 Read-Modify-Write Operations ......................................... 319 Reference Clock ................................................................. 71 Associated Registers .................................................. 73 Registers ADCON0 (ADC Control 0) ........................................ 139 ADCON1 (ADC Control 1) ........................................ 140 ADRESH (ADC Result High) with ADFM = 0) .......... 141 ADRESH (ADC Result High) with ADFM = 1) .......... 142 ADRESL (ADC Result Low) with ADFM = 0)............ 141 ADRESL (ADC Result Low) with ADFM = 1)............ 142 ANSELA (PORTA Analog Select)............................. 122 ANSELC (PORTC Analog Select) ............................ 126 APFCON0 (Alternate Pin Function Control 0) .......... 118 BAUDCON (Baud Rate Control)............................... 290 BORCON Brown-out Reset Control) .......................... 77 CCP1AS (CCP1 Auto-Shutdown Control) ................ 222 CCPxCON (ECCPx Control)..................................... 221 CLKRCON (Reference Clock Control)........................ 72 CMOUT (Comparator Output) .................................. 166 CMxCON0 (Cx Control) ............................................ 165 CMxCON1 (Cx Control 1) ......................................... 166 Configuration Word 1.................................................. 50 Configuration Word 2.................................................. 52
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/PWM (ECCP)...................................................................... 208 Packaging ......................................................................... 371 Marking ............................................................. 371, 372 PDIP Details.............................................................. 373 PCL and PCLATH ............................................................... 20 PCL Register........... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 PCLATH Register.... 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41 PCON Register ............................................................. 32, 81 PICSTART Plus Development Programmer ..................... 370 PIE1 Register ................................................................ 32, 90 PIE2 Register ...................................................................... 91 Pinout Descriptions PIC16F/LF1826/27................................................ 13, 15
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CPSCON0 (Capacitive Sensing Control Register 0) ........................................................ 313 CPSCON1 (Capacitive Sensing Control Register 1) 314 DACCON0 ................................................................ 151 DACCON1 ................................................................ 151 EEADRL (EEPROM Address) .................................. 114 EECON1 (EEPROM Control 1)................................. 115 EECON2 (EEPROM Control 2)................................. 116 EEDATH (EEPROM Data)........................................ 114 EEDATL (EEPROM Data) ........................................ 114 FVRCON................................................................... 132 INTCON (Interrupt Control)......................................... 89 IOCAF (Interrupt-on-Change PORTA Flag).............. 128 IOCAN (Interrupt-on-Change PORTA Negative Edge) ................................................. 128 IOCAP (Interrupt-on-Change PORTA Positive Edge)................................................... 128 LATA (Data Latch PORTA)....................................... 122 LATC (Data Latch PORTC) ...................................... 125 MDCARH (Modulation High Carrier Control Register)............................................... 196 MDCARL (Modulation Low Carrier Control Register)............................................... 197 MDCON (Modulation Control Register) .................... 194 MDSRC (Modulation Source Control Register) ........ 195 OPTION_REG (OPTION) ......................................... 171 OSCCON (Oscillator Control) ..................................... 68 OSCSTAT (Oscillator Status) ..................................... 69 OSCTUNE (Oscillator Tuning) .................................... 70 PCON (Power Control Register) ................................. 81 PCON (Power Control) ............................................... 81 PIE1 (Peripheral Interrupt Enable 1)........................... 90 PIE2 (Peripheral Interrupt Enable 2)........................... 91 PIR1 (Peripheral Interrupt Register 1) ........................ 92 PIR2 (Peripheral Interrupt Request 2) ........................ 93 PORTA...................................................................... 121 PORTC ..................................................................... 125 PSTRxCON (PWM Steering Control) ....................... 224 PWM1CON (Enhanced PWM Control) ..................... 223 RCREG ..................................................................... 296 RCSTA (Receive Status and Control)....................... 289 SPBRGH................................................................... 291 SPBRGL ................................................................... 291 Special Function, Summary ........................................ 31 SRCON0 (SR Latch Control 0) ................................. 155 SRCON1 (SR Latch Control 1) ................................. 156 SSPxADD (MSSPx Address and Baud Rate, I2C Mode) ......................................................... 278 SSPxCON1 (MSSPx Control 1) ................................ 275 SSPxCON2 (SSPx Control 2) ................................... 276 SSPxCON3 (SSPx Control 3) ................................... 277 SSPxMSK (SSPx Mask) ........................................... 278 SSPxSTAT (SSPx Status) ........................................ 274 STATUS...................................................................... 24 T1CON (Timer1 Control)........................................... 180 T1GCON (Timer1 Gate Control) ............................... 181 T2CON...................................................................... 186 TRISA (Tri-State PORTA)......................................... 121 TRISC (Tri-State PORTC) ........................................ 125 TXSTA (Transmit Status and Control) ...................... 288 WDTCON (Watchdog Timer Control) ....................... 101 WPUB (Weak Pull-up PORTB) ................................. 123 WPUC (Weak Pull-up PORTC)................................. 126 RESET .............................................................................. 329 Reset................................................................................... 75 Reset Instruction................................................................. 78 Resets ................................................................................ 75 Associated Registers.................................................. 82 Revision History................................................................ 387
S
Shoot-through Current ...................................................... 217 Software Simulator (MPLAB SIM) .................................... 368 SPBRG Register................................................................. 34 SPBRGH Register ............................................................ 291 SPBRGL Register............................................................. 291 Special Event Trigger ....................................................... 137 Special Function Registers (SFRs)..................................... 31 SPI Mode (MSSPx) Associated Registers................................................ 236 SPI Clock.................................................................. 232 SR Latch ........................................................................... 153 Associated registers w/ SR Latch............................. 157 SRCON0 Register ............................................................ 155 SRCON1 Register ............................................................ 156 SSP1ADD Register............................................................. 35 SSP1BUF Register ............................................................. 35 SSP1CON Register ............................................................ 35 SSP1CON2 Register .......................................................... 35 SSP1CON3 Register .......................................................... 35 SSP1MSK Register ............................................................ 35 SSP1STAT Register ........................................................... 35 SSPxADD Register........................................................... 278 SSPxCON1 Register ........................................................ 275 SSPxCON2 Register ........................................................ 276 SSPxCON3 Register ........................................................ 277 SSPxMSK Register........................................................... 278 SSPxOV ........................................................................... 263 SSPxOV Status Flag ........................................................ 263 SSPxSTAT Register ......................................................... 274 R/W Bit ..................................................................... 242 Stack................................................................................... 43 Accessing ................................................................... 43 Reset .......................................................................... 45 Stack Overflow/Underflow .................................................. 78 STATUS Register ............................................................... 24 SUBWFB .......................................................................... 331
T
T1CON Register ......................................................... 31, 180 T1GCON Register ............................................................ 181 T2CON (Timer2) Register................................................. 186 T2CON Register ................................................................. 31 Thermal Considerations.................................................... 346 Timer0 .............................................................................. 169 Associated Registers................................................ 171 Operation.................................................................. 169 Specifications ........................................................... 354 Timer1 .............................................................................. 172 Associated registers ................................................. 182 Asynchronous Counter Mode ................................... 174 Reading and Writing ......................................... 174 Clock Source Selection ............................................ 173 Interrupt .................................................................... 176 Operation.................................................................. 173 Operation During Sleep ............................................ 176 Oscillator................................................................... 174 Prescaler .................................................................. 174 Specifications ........................................................... 354 Timer1 Gate Selecting Source .............................................. 174
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TMR1H Register ....................................................... 172 TMR1L Register ........................................................ 172 Timer2 ............................................................................... 184 Associated registers.................................................. 187 Timer2/4/6 Associated registers.................................................. 187 Timers Timer1 T1CON.............................................................. 180 T1GCON ........................................................... 181 Timer2 T2CON.............................................................. 186 Timing Diagrams A/D Conversion ......................................................... 356 A/D Conversion (Sleep Mode) .................................. 356 Acknowledge Sequence ........................................... 265 Asynchronous Reception .......................................... 286 Asynchronous Transmission ..................................... 282 Asynchronous Transmission (Back to Back) ............ 282 Auto Wake-up Bit (WUE) During Normal Operation . 298 Auto Wake-up Bit (WUE) During Sleep .................... 298 Automatic Baud Rate Calibration .............................. 296 Baud Rate Generator with Clock Arbitration ............. 258 BRG Reset Due to SDA Arbitration During Start Condition........................................................... 269 Brown-out Reset (BOR) ............................................ 352 Brown-out Reset Situations ........................................ 77 Bus Collision During a Repeated Start Condition (Case 1) ............................................................ 270 Bus Collision During a Repeated Start Condition (Case 2) ............................................................ 270 Bus Collision During a Start Condition (SCL = 0) ..... 269 Bus Collision During a Stop Condition (Case 1) ....... 271 Bus Collision During a Stop Condition (Case 2) ....... 271 Bus Collision During Start Condition (SDA only) ...... 268 Bus Collision for Transmit and Acknowledge............ 267 CLKOUT and I/O....................................................... 350 Clock Synchronization .............................................. 255 Clock Timing ............................................................. 348 Comparator Output ................................................... 159 Enhanced Capture/Compare/PWM (ECCP) ............. 354 Fail-Safe Clock Monitor (FSCM) ................................. 67 First Start Bit Timing ................................................. 259 Full-Bridge PWM Output ........................................... 213 Half-Bridge PWM Output .................................. 211, 217 I2C Bus Data ............................................................. 362 I2C Bus Start/Stop Bits.............................................. 361 I2C Master Mode (7 or 10-Bit Transmission) ............ 262 I2C Master Mode (7-Bit Reception) ........................... 264 I2C Stop Condition Receive or Transmit Mode ......... 266 INT Pin Interrupt.......................................................... 87 Internal Oscillator Switch Timing................................. 62 PWM Auto-shutdown ................................................ 216 Firmware Restart .............................................. 216 PWM Direction Change ............................................ 214 PWM Direction Change at Near 100% Duty Cycle ... 215 PWM Output (Active-High)........................................ 209 PWM Output (Active-Low) ........................................ 210 Repeat Start Condition.............................................. 260 Reset Start-up Sequence............................................ 79 Reset, WDT, OST and Power-up Timer ................... 351 Send Break Character Sequence ............................. 299 SPI Master Mode (CKE = 1, SMP = 1) ..................... 359 SPI Mode (Master Mode) .......................................... 232 SPI Slave Mode (CKE = 0) ....................................... 360 SPI Slave Mode (CKE = 1) ....................................... 360 Synchronous Reception (Master Mode, SREN) ....... 303 Synchronous Transmission ...................................... 301 Synchronous Transmission (Through TXEN) ........... 301 Timer0 and Timer1 External Clock ........................... 353 Timer1 Incrementing Edge ....................................... 176 Two Speed Start-up.................................................... 65 USART Synchronous Receive (Master/Slave) ......... 358 USART Synchronous Transmission (Master/Slave) .................................................. 358 Wake-up from Interrupt............................................... 96 Timing Diagrams and Specifications PLL Clock ................................................................. 349 Timing Parameter Symbology .......................................... 347 Timing Requirements I2C Bus Data............................................................. 363 SPI Mode .................................................................. 361 TMR0 Register.................................................................... 31 TMR1H Register ................................................................. 31 TMR1L Register.................................................................. 31 TMR2 Register.................................................................... 31 TRIS.................................................................................. 332 TRISA Register........................................................... 32, 121 TRISC Register........................................................... 32, 125 Two-Speed Clock Start-up Mode........................................ 64 TXREG ............................................................................. 281 TXREG Register ................................................................. 34 TXSTA Register.......................................................... 34, 288 BRGH Bit .................................................................. 291
U
USART Synchronous Master Mode Requirements, Synchronous Receive .............. 358 Requirements, Synchronous Transmission...... 358 Timing Diagram, Synchronous Receive ........... 358 Timing Diagram, Synchronous Transmission... 358
V
VREF. SEE ADC Reference Voltage
W
Wake-up on Break ............................................................ 297 Wake-up Using Interrupts ................................................... 96 Watchdog Timer (WDT)...................................................... 78 Modes ....................................................................... 100 Specifications ........................................................... 353 WCOL ....................................................... 258, 261, 263, 265 WCOL Status Flag.................................... 258, 261, 263, 265 WDTCON Register ........................................................... 101 WPUB Register................................................................. 123 WPUC Register ................................................................ 126 Write Protection .................................................................. 53 WWW Address ................................................................. 395 WWW, On-Line Support ..................................................... 10
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4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41413A-page 396
Preliminary
2010 Microchip Technology Inc.
PIC12F/LF1822/16F/LF1823
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC12F1822(1), PIC16F1823(1), PIC12F1822T(2), PIC16F1823T(2); VDD range 1.8V to 5.5V PIC12LF1822(1), PIC16LF1823(1), PIC12LF1822T(2), PIC16LF1823T(2); VDD range 1.8V to 3.6V I E MF ML P SL SN SS ST = = = = = = = = -40C to +85C = -40C to +125C (Industrial) (Extended) c) PIC12F1822 - I/ML 301 = Industrial temp., QFN package, Extended VDD limits, QTP pattern #301. PIC16F1823 - I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F1823 - E/SS= Extended temp., SSOP package, normal VDD limits.
Temperature Range: Package:
Micro Lead Frame (DFN) 3x3 Micro Lead Frame (QFN) 6x6 Plastic DIP SOIC, 14 lead SOIC, 8 lead SSOP TSSOP
Note 1: 2:
F = Wide Voltage Range LF = Standard Voltage Range T = in tape and reel SOIC, SSOP, TSSOP, and QFN packages only.
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
2010 Microchip Technology Inc.
Preliminary
DS41413A-page 397
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/05/10
DS41413A-page 398
Preliminary
2010 Microchip Technology Inc.

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